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nvgpu: Add dummy variables to accomodate PS3.5 structure

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Change-Id: I437f2aba6a63de87033721fa9a29c565cf8f4256
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1694546
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vaikundanathan S
2018-04-13 14:39:07 +05:30
committed by mobile promotions
parent 85f9729af4
commit ea46b46cd1
3 changed files with 25 additions and 2 deletions
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2
drivers/gpu/nvgpu/ctrl/ctrlclkavfs.h
View File

@@ -59,7 +59,7 @@
BIT(CTRL_CLK_VIN_ID_GPC3) | \
BIT(CTRL_CLK_VIN_ID_GPC4) | \
BIT(CTRL_CLK_VIN_ID_GPC5))
#define CTRL_CLK_LUT_NUM_ENTRIES 0x50
#define CTRL_CLK_LUT_NUM_ENTRIES (100)
#define CTRL_CLK_VIN_STEP_SIZE_UV (10000)
#define CTRL_CLK_LUT_MIN_VOLTAGE_UV (450000)
#define CTRL_CLK_FLL_TYPE_DISABLED 0

3
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
View File

@@ -50,12 +50,13 @@ struct nv_pmu_super_surface {
struct nv_pmu_clk_clk_vin_device_boardobj_grp_set clk_vin_device_grp_set;
struct nv_pmu_clk_clk_domain_boardobj_grp_set clk_domain_grp_set;
struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set clk_freq_controller_grp_set;
u8 clk_rsvd2[0x200];
struct nv_pmu_clk_clk_fll_device_boardobj_grp_set clk_fll_device_grp_set;
struct nv_pmu_clk_clk_prog_boardobj_grp_set clk_prog_grp_set;
struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set;
struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status;
struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status;
u8 clk_rsvd1[0x800];
struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status;
u8 clk_rsvd[0x4660];
} clk;

22
drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
View File

@@ -128,12 +128,30 @@ struct nv_pmu_clk_clk_domain_3x_master_boardobj_set {
u32 slave_idxs_mask;
};
struct nv_pmu_clk_clk_domain_35_prog_boardobj_set {
struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
u8 dummy;
};
struct nv_pmu_clk_clk_domain_35_master_boardobj_set {
struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
u32 master_slave_domains_grp_mask;
};
struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set {
struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super;
u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
u8 master_idx;
};
struct nv_pmu_clk_clk_domain_35_slave_boardobj_set {
struct nv_pmu_clk_clk_domain_35_prog_boardobj_set super;
u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */
u8 master_idx;
};
union nv_pmu_clk_clk_domain_boardobj_set_union {
struct nv_pmu_boardobj board_obj;
struct nv_pmu_clk_clk_domain_boardobj_set super;
@@ -142,6 +160,9 @@ union nv_pmu_clk_clk_domain_boardobj_set_union {
struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog;
struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master;
struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave;
struct nv_pmu_clk_clk_domain_35_prog_boardobj_set v35_prog;
struct nv_pmu_clk_clk_domain_35_master_boardobj_set v35_master;
struct nv_pmu_clk_clk_domain_35_slave_boardobj_set v35_slave;
};
NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain);
@@ -504,6 +525,7 @@ struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header {
struct nv_pmu_clk_clk_fll_device_boardobj_get_status {
struct nv_pmu_boardobj_query super;
u8 current_regime_id;
bool b_dvco_min_reached;
u16 min_freq_mhz;
struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)];
};