nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: gv11b: use read_engine_status_info gops for preempt poll

Browse Source 
Use read_engine_status_info hal to read engine status and use
NVGPU_CTX_STATUS_* for engine ctxsw_status check instead of
directly reading h/w registers and field defs. This will make
gv11b preempt driver usable for nvgpu-next.

JIRA NVGPU-4982

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Id063f9791f38715aed3a9c7999fd253b1bc2bc87
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2311276
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
2020-03-11 17:18:22 -07:00
committed by Alex Waterman
parent f91495c41d
commit ebb91f0b4d
1 changed files with 15 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
drivers/gpu/nvgpu/hal/fifo/preempt_gv11b_fusa.c
View File

@@ -233,13 +233,14 @@ int gv11b_fifo_preempt_poll_pbdma(struct gk20a *g, u32 tsgid,
return ret;
}
static int fifo_check_eng_intr_pending(struct gk20a *g, u32 id,
u32 eng_stat, u32 ctx_stat, u32 eng_intr_pending,
u32 engine_id, u32 *reset_eng_bitmask)
static int gv11b_fifo_check_eng_intr_pending(struct gk20a *g, u32 id,
struct nvgpu_engine_status_info *engine_status,
u32 eng_intr_pending,
u32 engine_id, u32 *reset_eng_bitmask)
{
int ret = -EBUSY;
if (ctx_stat == fifo_engine_status_ctx_status_ctxsw_switch_v()) {
if (engine_status->ctxsw_status == NVGPU_CTX_STATUS_CTXSW_SWITCH) {
/* Eng save hasn't started yet. Continue polling */
if (eng_intr_pending != 0U) {
/* if eng intr, stop polling */
@@ -247,10 +248,10 @@ static int fifo_check_eng_intr_pending(struct gk20a *g, u32 id,
ret = 0;
}
} else if ((ctx_stat == fifo_engine_status_ctx_status_valid_v()) ||
(ctx_stat == fifo_engine_status_ctx_status_ctxsw_save_v())) {
} else if ((engine_status->ctxsw_status == NVGPU_CTX_STATUS_VALID) ||
(engine_status->ctxsw_status == NVGPU_CTX_STATUS_CTXSW_SAVE)) {
if (id == fifo_engine_status_id_v(eng_stat)) {
if (id == engine_status->ctx_id) {
if (eng_intr_pending != 0U) {
/* preemption will not finish */
*reset_eng_bitmask |= BIT32(engine_id);
@@ -261,9 +262,9 @@ static int fifo_check_eng_intr_pending(struct gk20a *g, u32 id,
ret = 0;
}
} else if (ctx_stat == fifo_engine_status_ctx_status_ctxsw_load_v()) {
} else if (engine_status->ctxsw_status == NVGPU_CTX_STATUS_CTXSW_LOAD) {
if (id == fifo_engine_status_next_id_v(eng_stat)) {
if (id == engine_status->ctx_next_id) {
if (eng_intr_pending != 0U) {
/* preemption will not finish */
*reset_eng_bitmask |= BIT32(engine_id);
@@ -273,7 +274,6 @@ static int fifo_check_eng_intr_pending(struct gk20a *g, u32 id,
/* context is not running on the engine */
ret = 0;
}
} else {
/* Preempt should be finished */
ret = 0;
@@ -287,11 +287,10 @@ static int gv11b_fifo_preempt_poll_eng(struct gk20a *g, u32 id,
{
struct nvgpu_timeout timeout;
u32 delay = POLL_DELAY_MIN_US;
u32 eng_stat;
u32 ctx_stat;
int ret;
unsigned int loop_count = 0;
u32 eng_intr_pending;
struct nvgpu_engine_status_info engine_status;
/* timeout in milli seconds */
ret = nvgpu_timeout_init(g, &timeout,
@@ -317,8 +316,8 @@ static int gv11b_fifo_preempt_poll_eng(struct gk20a *g, u32 id,
}
loop_count++;
}
eng_stat = nvgpu_readl(g, fifo_engine_status_r(engine_id));
ctx_stat = fifo_engine_status_ctx_status_v(eng_stat);
g->ops.engine_status.read_engine_status_info(g,
engine_id, &engine_status);
if (g->ops.mc.is_stall_and_eng_intr_pending(g, engine_id,
&eng_intr_pending)) {
@@ -355,7 +354,7 @@ static int gv11b_fifo_preempt_poll_eng(struct gk20a *g, u32 id,
"stall intr set, "
"preemption might not finish");
}
ret = fifo_check_eng_intr_pending(g, id, eng_stat, ctx_stat,
ret = gv11b_fifo_check_eng_intr_pending(g, id, &engine_status,
eng_intr_pending, engine_id,
reset_eng_bitmask);
if (ret == 0) {
@@ -375,7 +374,7 @@ static int gv11b_fifo_preempt_poll_eng(struct gk20a *g, u32 id,
* 3.The engine hangs during CTXSW.
*/
nvgpu_err(g, "preempt timeout eng: %u ctx_stat: %u tsgid: %u",
engine_id, ctx_stat, id);
engine_id, engine_status.ctxsw_status, id);
*reset_eng_bitmask |= BIT32(engine_id);
}