gpu: nvgpu: move syncpt specific cmdbuf methods to common/sync/

syncpt cmdbuf specific functions are only for the sync functionality of
nvgpu and donot belong to fifo.

construct files syncpt_cmdbuf_gk20a.h and syncpt_cmdbuf_gk20a.c under
common/sync to contain the syncpt specific cmdbuf functions for arch
gk20a.

The word 'fifo' is also removed from the name of these functions.

Jira NVGPU-1308

Change-Id: I1a1fd1d31f7decd1398f8e2ff625f95cf1f55033
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1975920
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -243,7 +243,8 @@ nvgpu-$(CONFIG_GK20A_PCI) += \
 	os/linux/pci_usermode.o
 
 nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += \
-	os/linux/nvhost.o
+	os/linux/nvhost.o \
+	common/sync/syncpt_cmdbuf_gk20a.o
 
 nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
 	os/linux/vgpu/platform_vgpu_tegra.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -160,6 +160,7 @@ srcs += common/sim.c \
 	common/sync/channel_sync.c \
 	common/sync/channel_sync_syncpt.c \
 	common/sync/channel_sync_semaphore.c \
+	common/sync/syncpt_cmdbuf_gk20a.c \
 	common/clock_gating/gm20b_gating_reglist.c \
 	common/clock_gating/gp10b_gating_reglist.c \
 	common/clock_gating/gv11b_gating_reglist.c \

drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gk20a.c

@@ -0,0 +1,104 @@
+/*
+ * GK20A syncpt cmdbuf
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/channel.h>
+
+#include "syncpt_cmdbuf_gk20a.h"
+
+void gk20a_add_syncpt_wait_cmd(struct gk20a *g,
+		struct priv_cmd_entry *cmd, u32 off,
+		u32 id, u32 thresh, u64 gpu_va)
+{
+	nvgpu_log_fn(g, " ");
+
+	off = cmd->off + off;
+	/* syncpoint_a */
+	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001CU);
+	/* payload */
+	nvgpu_mem_wr32(g, cmd->mem, off++, thresh);
+	/* syncpoint_b */
+	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
+	/* syncpt_id, switch_en, wait */
+	nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x10U);
+}
+
+u32 gk20a_get_syncpt_wait_cmd_size(void)
+{
+	return 4U;
+}
+
+u32 gk20a_get_syncpt_incr_per_release(void)
+{
+	return 2U;
+}
+
+void gk20a_add_syncpt_incr_cmd(struct gk20a *g,
+		bool wfi_cmd, struct priv_cmd_entry *cmd,
+		u32 id, u64 gpu_va)
+{
+	u32 off = cmd->off;
+
+	nvgpu_log_fn(g, " ");
+	if (wfi_cmd) {
+		/* wfi */
+		nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001EU);
+		/* handle, ignored */
+		nvgpu_mem_wr32(g, cmd->mem, off++, 0x00000000U);
+	}
+	/* syncpoint_a */
+	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001CU);
+	/* payload, ignored */
+	nvgpu_mem_wr32(g, cmd->mem, off++, 0U);
+	/* syncpoint_b */
+	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
+	/* syncpt_id, incr */
+	nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x1U);
+	/* syncpoint_b */
+	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
+	/* syncpt_id, incr */
+	nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x1U);
+
+}
+
+u32 gk20a_get_syncpt_incr_cmd_size(bool wfi_cmd)
+{
+	if (wfi_cmd)
+		return 8U;
+	else
+		return 6U;
+}
+
+void gk20a_free_syncpt_buf(struct channel_gk20a *c,
+		struct nvgpu_mem *syncpt_buf)
+{
+
+}
+
+int gk20a_alloc_syncpt_buf(struct channel_gk20a *c,
+		u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
+{
+	return 0;
+}

drivers/gpu/nvgpu/common/sync/syncpt_cmdbuf_gk20a.h

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_SYNC_SYNCPT_CMDBUF_GK20A_H
+#define NVGPU_SYNC_SYNCPT_CMDBUF_GK20A_H
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct priv_cmd_entry;
+struct nvgpu_mem;
+
+#ifdef CONFIG_TEGRA_GK20A_NVHOST
+
+void gk20a_add_syncpt_wait_cmd(struct gk20a *g,
+		struct priv_cmd_entry *cmd, u32 off,
+		u32 id, u32 thresh, u64 gpu_va);
+u32 gk20a_get_syncpt_wait_cmd_size(void);
+u32 gk20a_get_syncpt_incr_per_release(void);
+void gk20a_add_syncpt_incr_cmd(struct gk20a *g,
+		bool wfi_cmd, struct priv_cmd_entry *cmd,
+		u32 id, u64 gpu_va);
+u32 gk20a_get_syncpt_incr_cmd_size(bool wfi_cmd);
+void gk20a_free_syncpt_buf(struct channel_gk20a *c,
+		struct nvgpu_mem *syncpt_buf);
+
+int gk20a_alloc_syncpt_buf(struct channel_gk20a *c,
+		u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
+
+#else
+
+static inline void gk20a_add_syncpt_wait_cmd(struct gk20a *g,
+		struct priv_cmd_entry *cmd, u32 off,
+		u32 id, u32 thresh, u64 gpu_va)
+{
+}
+static inline u32 gk20a_get_syncpt_wait_cmd_size(void)
+{
+	return 0U;
+}
+static inline u32 gk20a_get_syncpt_incr_per_release(void)
+{
+	return 0U;
+}
+static inline void gk20a_add_syncpt_incr_cmd(struct gk20a *g,
+		bool wfi_cmd, struct priv_cmd_entry *cmd,
+		u32 id, u64 gpu_va)
+{
+}
+static inline u32 gk20a_get_syncpt_incr_cmd_size(bool wfi_cmd)
+{
+	return 0U;
+}
+static inline void gk20a_free_syncpt_buf(struct channel_gk20a *c,
+		struct nvgpu_mem *syncpt_buf)
+{
+}
+
+static inline int gk20a_alloc_syncpt_buf(struct channel_gk20a *c,
+		u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
+{
+	return -ENOSYS;
+}
+
+#endif
+
+#endif /* NVGPU_SYNC_SYNCPT_CMDBUF_GK20A_H */

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -3541,80 +3541,3 @@ bool gk20a_fifo_find_pbdma_for_runlist(struct fifo_gk20a *f, u32 runlist_id,
 	*pbdma_id = id;
 	return found_pbdma_for_runlist;
 }
-
-#ifdef CONFIG_TEGRA_GK20A_NVHOST
-void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g,
-		struct priv_cmd_entry *cmd, u32 off,
-		u32 id, u32 thresh, u64 gpu_va)
-{
-	nvgpu_log_fn(g, " ");
-
-	off = cmd->off + off;
-	/* syncpoint_a */
-	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001CU);
-	/* payload */
-	nvgpu_mem_wr32(g, cmd->mem, off++, thresh);
-	/* syncpoint_b */
-	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
-	/* syncpt_id, switch_en, wait */
-	nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x10U);
-}
-
-u32 gk20a_fifo_get_syncpt_wait_cmd_size(void)
-{
-	return 4;
-}
-
-u32 gk20a_fifo_get_syncpt_incr_per_release(void)
-{
-	return 2;
-}
-
-void gk20a_fifo_add_syncpt_incr_cmd(struct gk20a *g,
-		bool wfi_cmd, struct priv_cmd_entry *cmd,
-		u32 id, u64 gpu_va)
-{
-	u32 off = cmd->off;
-
-	nvgpu_log_fn(g, " ");
-	if (wfi_cmd) {
-		/* wfi */
-		nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001EU);
-		/* handle, ignored */
-		nvgpu_mem_wr32(g, cmd->mem, off++, 0x00000000U);
-	}
-	/* syncpoint_a */
-	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001CU);
-	/* payload, ignored */
-	nvgpu_mem_wr32(g, cmd->mem, off++, 0U);
-	/* syncpoint_b */
-	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
-	/* syncpt_id, incr */
-	nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x1U);
-	/* syncpoint_b */
-	nvgpu_mem_wr32(g, cmd->mem, off++, 0x2001001DU);
-	/* syncpt_id, incr */
-	nvgpu_mem_wr32(g, cmd->mem, off++, (id << 8U) | 0x1U);
-
-}
-
-u32 gk20a_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd)
-{
-	if (wfi_cmd)
-		return 8;
-	else
-		return 6;
-}
-
-void gk20a_fifo_free_syncpt_buf(struct channel_gk20a *c,
-				struct nvgpu_mem *syncpt_buf)
-{
-
-}
-
-int gk20a_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
-			u32 syncpt_id, struct nvgpu_mem *syncpt_buf)
-{
-	return 0;
-}
-#endif

drivers/gpu/nvgpu/gk20a/fifo_gk20a.h

@@ -407,22 +407,6 @@ u32 gk20a_fifo_handle_pbdma_intr(struct gk20a *g, struct fifo_gk20a *f,
 
 u32 gk20a_fifo_default_timeslice_us(struct gk20a *g);
 
-#ifdef CONFIG_TEGRA_GK20A_NVHOST
-void gk20a_fifo_add_syncpt_wait_cmd(struct gk20a *g,
-			struct priv_cmd_entry *cmd, u32 off,
-			u32 id, u32 thresh, u64 gpu_va);
-u32 gk20a_fifo_get_syncpt_wait_cmd_size(void);
-u32 gk20a_fifo_get_syncpt_incr_per_release(void);
-void gk20a_fifo_add_syncpt_incr_cmd(struct gk20a *g,
-			bool wfi_cmd, struct priv_cmd_entry *cmd,
-			u32 id, u64 gpu_va);
-u32 gk20a_fifo_get_syncpt_incr_cmd_size(bool wfi_cmd);
-void gk20a_fifo_free_syncpt_buf(struct channel_gk20a *c,
-			struct nvgpu_mem *syncpt_buf);
-int gk20a_fifo_alloc_syncpt_buf(struct channel_gk20a *c,
-			u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
-#endif
-
 void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id,
 				struct mmu_fault_info *mmfault);
 void gk20a_fifo_get_mmu_fault_desc(struct mmu_fault_info *mmfault);

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -54,6 +54,7 @@
 #include "common/pmu/acr_gm20b.h"
 #include "common/falcon/falcon_gk20a.h"
 #include "common/top/top_gm20b.h"
+#include "common/sync/syncpt_cmdbuf_gk20a.h"
 #include "common/regops/regops_gm20b.h"
 #include "common/fifo/runlist_gk20a.h"
 
@@ -538,14 +539,14 @@ static const struct gpu_ops gm20b_ops = {
 	},
 	.sync = {
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
-		.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
-		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
-		.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
+		.alloc_syncpt_buf = gk20a_alloc_syncpt_buf,
+		.free_syncpt_buf = gk20a_free_syncpt_buf,
+		.add_syncpt_wait_cmd = gk20a_add_syncpt_wait_cmd,
 		.get_syncpt_incr_per_release =
-				gk20a_fifo_get_syncpt_incr_per_release,
-		.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
-		.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
-		.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
+				gk20a_get_syncpt_incr_per_release,
+		.get_syncpt_wait_cmd_size = gk20a_get_syncpt_wait_cmd_size,
+		.add_syncpt_incr_cmd = gk20a_add_syncpt_incr_cmd,
+		.get_syncpt_incr_cmd_size = gk20a_get_syncpt_incr_cmd_size,
 		.get_sync_ro_map = NULL,
 #endif
 		.get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size,

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -65,6 +65,7 @@
 #include "common/falcon/falcon_gk20a.h"
 #include "common/top/top_gm20b.h"
 #include "common/top/top_gp10b.h"
+#include "common/sync/syncpt_cmdbuf_gk20a.h"
 #include "common/regops/regops_gp10b.h"
 #include "common/fifo/runlist_gk20a.h"
 
@@ -588,14 +589,14 @@ static const struct gpu_ops gp10b_ops = {
 	},
 	.sync = {
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
-		.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
-		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
-		.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
+		.alloc_syncpt_buf = gk20a_alloc_syncpt_buf,
+		.free_syncpt_buf = gk20a_free_syncpt_buf,
+		.add_syncpt_wait_cmd = gk20a_add_syncpt_wait_cmd,
 		.get_syncpt_incr_per_release =
-				gk20a_fifo_get_syncpt_incr_per_release,
-		.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
-		.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
-		.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
+				gk20a_get_syncpt_incr_per_release,
+		.get_syncpt_wait_cmd_size = gk20a_get_syncpt_wait_cmd_size,
+		.add_syncpt_incr_cmd = gk20a_add_syncpt_incr_cmd,
+		.get_syncpt_incr_cmd_size = gk20a_get_syncpt_incr_cmd_size,
 		.get_sync_ro_map = NULL,
 #endif
 		.get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size,

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -54,6 +54,7 @@
 #include "vgpu_fuse_gp10b.h"
 
 #include "common/falcon/falcon_gk20a.h"
+#include "common/sync/syncpt_cmdbuf_gk20a.h"
 
 #include "gp10b/mm_gp10b.h"
 #include "gp10b/ce_gp10b.h"
@@ -409,14 +410,14 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 	},
 	.sync = {
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
-		.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
-		.free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
-		.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
-		.get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
+		.alloc_syncpt_buf = gk20a_alloc_syncpt_buf,
+		.free_syncpt_buf = gk20a_free_syncpt_buf,
+		.add_syncpt_wait_cmd = gk20a_add_syncpt_wait_cmd,
+		.get_syncpt_wait_cmd_size = gk20a_get_syncpt_wait_cmd_size,
 		.get_syncpt_incr_per_release =
-				gk20a_fifo_get_syncpt_incr_per_release,
-		.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
-		.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
+				gk20a_get_syncpt_incr_per_release,
+		.add_syncpt_incr_cmd = gk20a_add_syncpt_incr_cmd,
+		.get_syncpt_incr_cmd_size = gk20a_get_syncpt_incr_cmd_size,
 		.get_sync_ro_map = NULL,
 #endif
 		.get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size,