gpu: nvgpu: Add support to query dgpu max freq

Implement get_maxrate for TU104.
This function will use the clk_arb to get the P0 Max from VBIOS.

Bug 2610308

Change-Id: I09c692676bf949f300c9edd00f4faa26118b124f
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133427
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/hal/clk/clk_gv100.c

@@ -34,6 +34,7 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/gk20a.h>
 #include <nvgpu/clk.h>
+#include <nvgpu/clk_arb.h>
 #include <nvgpu/pmu/clk/clk.h>
 #include <nvgpu/pmu/clk/clk_domain.h>
 #include <nvgpu/hw/gv100/hw_trim_gv100.h>
@@ -234,3 +235,18 @@ void gv100_suspend_clk_support(struct gk20a *g)
 {
 	nvgpu_mutex_destroy(&g->clk.clk_mutex);
 }
+
+unsigned long gv100_clk_maxrate(struct gk20a *g, u32 api_domain)
+{
+	u16 min_mhz, max_mhz;
+	int status;
+
+	status = nvgpu_clk_arb_get_arbiter_clk_range(g, api_domain, &min_mhz,
+			&max_mhz);
+	if (status != 0) {
+		nvgpu_err(g, "failed to fetch clock range");
+		return 0U;
+	}
+
+	return (max_mhz * 1000UL * 1000UL);
+}

drivers/gpu/nvgpu/hal/clk/clk_gv100.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -35,4 +35,5 @@ int gv100_clk_domain_get_f_points(
 	u32 clkapidomain,
 	u32 *pfpointscount,
 	u16 *pfreqpointsinmhz);
+unsigned long gv100_clk_maxrate(struct gk20a *g, u32 api_domain);
 #endif /* CLK_GV100_H */

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -1130,6 +1130,7 @@ static const struct gpu_ops tu104_ops = {
 		.suspend_clk_support = gv100_suspend_clk_support,
 		.perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35,
 		.clk_domain_get_f_points = gv100_clk_domain_get_f_points,
+		.get_maxrate = gv100_clk_maxrate,
 	},
 	.clk_arb = {
 		.check_clk_arb_support = gv100_check_clk_arb_support,

drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c

@@ -47,6 +47,7 @@
 #include <nvgpu/power_features/pg.h>
 #include <nvgpu/fence.h>
 #include <nvgpu/channel_sync_syncpt.h>
+#include <nvgpu/soc.h>
 
 #include "ioctl_ctrl.h"
 #include "ioctl_dbg.h"
@@ -376,8 +377,10 @@ gk20a_ctrl_ioctl_gpu_characteristics(
 	gpu.cbc_cache_line_size = nvgpu_ltc_get_cacheline_size(g);
 	gpu.cbc_comptags_per_line = g->cbc->comptags_per_cacheline;
 
-	if (g->ops.clk.get_maxrate)
-		gpu.max_freq = g->ops.clk.get_maxrate(g, CTRL_CLK_DOMAIN_GPCCLK);
+	if ((g->ops.clk.get_maxrate) && nvgpu_platform_is_silicon(g)) {
+		gpu.max_freq = g->ops.clk.get_maxrate(g,
+				CTRL_CLK_DOMAIN_GPCCLK);
+	}
 
 	gpu.local_video_memory_size = g->mm.vidmem.size;