gpu: nvgpu: Fix MISRA 15.7 violation in nvlink

MISRA 15.7 does not allow empty terminating "else" statement.
Fix such violations in nvlink by adding else clause.

JIRA NVGPU-1921

Change-Id: I29c276ac612adc56d7405c5e9b28ee4b41ba21fa
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2027262
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Tejal Kudav
2019-02-25 12:58:09 +05:30
committed by mobile promotions
parent f357136ff9
commit ec513e4a1a

View File

@@ -1387,13 +1387,10 @@ int gv100_nvlink_link_set_mode(struct gk20a *g, u32 link_id,
if (state == nvl_link_state_state_swcfg_v()) {
nvgpu_warn(g, "link is already in safe mode");
break;
}
if (state == nvl_link_state_state_hwcfg_v()) {
} else if (state == nvl_link_state_state_hwcfg_v()) {
nvgpu_warn(g, "link is transitioning to safe mode");
break;
}
if (state == nvl_link_state_state_init_v()) {
} else if (state == nvl_link_state_state_init_v()) {
/* Off to Safe transition */
reg = DLPL_REG_RD32(g, link_id, nvl_link_change_r());
reg = set_field(reg, nvl_link_change_newstate_m(),
@@ -1416,6 +1413,10 @@ int gv100_nvlink_link_set_mode(struct gk20a *g, u32 link_id,
reg = set_field(reg, nvl_link_change_action_m(),
nvl_link_change_action_ltssm_change_f());
DLPL_REG_WR32(g, link_id, nvl_link_change_r(), reg);
} else {
nvgpu_err(g,
"Link state transition to Safe mode not permitted");
return -EPERM;
}
break;
@@ -1544,8 +1545,7 @@ int gv100_nvlink_link_set_sublink_mode(struct gk20a *g, u32 link_id,
nvl_sl0_slsm_status_tx_primary_state_off_v()) {
nvgpu_err(g, "TX cannot be do from OFF to HS");
return -EPERM;
}
} else {
reg = DLPL_REG_RD32(g, link_id, nvl_sublink_change_r());
reg = set_field(reg, nvl_sublink_change_newstate_m(),
nvl_sublink_change_newstate_hs_f());
@@ -1560,6 +1560,7 @@ int gv100_nvlink_link_set_sublink_mode(struct gk20a *g, u32 link_id,
nvgpu_err(g, "Error in TX to HS");
return err;
}
}
break;
case nvgpu_nvlink_sublink_tx_common:
err = gv100_nvlink_minion_init_uphy(g, BIT64(link_id), true);
@@ -1604,8 +1605,7 @@ int gv100_nvlink_link_set_sublink_mode(struct gk20a *g, u32 link_id,
nvl_sl0_slsm_status_tx_primary_state_hs_v()) {
nvgpu_err(g, " TX cannot go off from HS %d", link_id);
return -EPERM;
}
} else {
reg = DLPL_REG_RD32(g, link_id, nvl_sublink_change_r());
reg = set_field(reg, nvl_sublink_change_newstate_m(),
nvl_sublink_change_newstate_off_f());
@@ -1620,6 +1620,7 @@ int gv100_nvlink_link_set_sublink_mode(struct gk20a *g, u32 link_id,
nvgpu_err(g, "Error in TX to OFF");
return err;
}
}
break;
/* RX modes */
@@ -1635,8 +1636,7 @@ int gv100_nvlink_link_set_sublink_mode(struct gk20a *g, u32 link_id,
nvl_sl1_slsm_status_rx_primary_state_hs_v()) {
nvgpu_err(g, " RX cannot go off from HS %d", link_id);
return -EPERM;
}
} else {
reg = DLPL_REG_RD32(g, link_id, nvl_sublink_change_r());
reg = set_field(reg, nvl_sublink_change_newstate_m(),
nvl_sublink_change_newstate_off_f());
@@ -1651,6 +1651,7 @@ int gv100_nvlink_link_set_sublink_mode(struct gk20a *g, u32 link_id,
nvgpu_err(g, "Error in RX to OFF");
return err;
}
}
break;
case nvgpu_nvlink_sublink_rx_rxcal:
err = gv100_nvlink_rxcal_en(g, BIT64(link_id));