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gpu: nvgpu: Restructure common.pmu.perf unit

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This patch does the following.
1. Remove unused functions from pmu_perf.c.
2. Append public functions with nvgpu.
3. Move get_status declaration from vfe_var to include/perf.
4. Rename perf_tu104.c to perf_ps35.c and Makefile changes.
5. Remove the unused perf_tu104.h file.
6. Make local functions as static.

Jira NVGPU-1960

Change-Id: I829d113d994dbfc02a45f29795b5926c58106049
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2023886
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Abdul Salam
2019-02-26 15:03:33 +05:30
committed by mobile promotions
parent ee9d992c14
commit f357136ff9
13 changed files with 33 additions and 171 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/nvgpu/Makefile
View File

@@ -128,7 +128,7 @@ nvgpu-y += \
common/pmu/perf/vfe_equ.o \
common/pmu/perf/pmu_perf.o \
common/pmu/perf/perf_gv100.o \
common/pmu/perf/perf_tu104.o \
common/pmu/perf/perf_ps35.o \
common/pmu/perf/change_seq.o \
common/pmu/pmgr/pwrdev.o \
common/pmu/pmgr/pmgr.o \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -240,7 +240,7 @@ srcs += common/sim.c \
common/pmu/perf/vfe_equ.c \
common/pmu/perf/vfe_var.c \
common/pmu/perf/perf_gv100.c \
common/pmu/perf/perf_tu104.c \
common/pmu/perf/perf_ps35.c \
common/pmu/perf/change_seq.c \
common/pmu/pmgr/pmgr.c \
common/pmu/pmgr/pmgrpmu.c \

2
drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.c
View File

@@ -82,7 +82,7 @@ static int gv100_pmu_handle_perf_event(struct gk20a *g, void *pmumsg)
return 0;
}
u32 perf_pmu_init_vfe_perf_event(struct gk20a *g)
static u32 perf_pmu_init_vfe_perf_event(struct gk20a *g)
{
struct perf_pmupstate *perf_pmu = g->perf_pmu;
char thread_name[64];

1
drivers/gpu/nvgpu/common/pmu/perf/perf_gv100.h
View File

@@ -29,7 +29,6 @@
struct gk20a;
u32 perf_pmu_init_vfe_perf_event(struct gk20a *g);
int gv100_perf_pmu_vfe_load(struct gk20a *g);
#endif /* NVGPU_PERF_GV100_H */

9
drivers/gpu/nvgpu/common/pmu/perf/perf_tu104.c → drivers/gpu/nvgpu/common/pmu/perf/perf_ps35.c
View File

@@ -28,7 +28,6 @@
#include <nvgpu/clk_arb.h>
#include <nvgpu/pmu/perf.h>
#include "perf_tu104.h"
#include "pmu_perf.h"
static int pmu_set_boot_clk_runcb_fn(void *arg)
@@ -85,7 +84,7 @@ static int tu104_pmu_handle_perf_event(struct gk20a *g, void *pmumsg)
return 0;
}
int tu104_perf_pmu_init_vfe_perf_event(struct gk20a *g)
static int perf_pmu_init_vfe_perf_event(struct gk20a *g)
{
struct perf_pmupstate *perf_pmu = g->perf_pmu;
char thread_name[64];
@@ -100,7 +99,7 @@ int tu104_perf_pmu_init_vfe_perf_event(struct gk20a *g)
err = nvgpu_thread_create(&perf_pmu->vfe_init.state_task, g,
pmu_set_boot_clk_runcb_fn, thread_name);
if (err != 0U) {
if (err != 0) {
nvgpu_err(g, "failed to start nvgpu_vfe_invalidate_init thread");
}
@@ -108,7 +107,7 @@ int tu104_perf_pmu_init_vfe_perf_event(struct gk20a *g)
}
int tu104_perf_pmu_vfe_load(struct gk20a *g)
int nvgpu_perf_pmu_vfe_load_ps35(struct gk20a *g)
{
struct nvgpu_pmu *pmu = &g->pmu;
struct nv_pmu_rpc_struct_perf_load rpc;
@@ -122,7 +121,7 @@ int tu104_perf_pmu_vfe_load(struct gk20a *g)
status);
}
status = tu104_perf_pmu_init_vfe_perf_event(g);
status = perf_pmu_init_vfe_perf_event(g);
/*register call back for future VFE updates*/
g->ops.pmu_perf.handle_pmu_perf_event = tu104_pmu_handle_perf_event;

35
drivers/gpu/nvgpu/common/pmu/perf/perf_tu104.h
View File

@@ -1,35 +0,0 @@
/*
* GV100 PERF
*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NVGPU_PERF_TU104_H
#define NVGPU_PERF_TU104_H
#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
struct gk20a;
int tu104_perf_pmu_init_vfe_perf_event(struct gk20a *g);
int tu104_perf_pmu_vfe_load(struct gk20a *g);
#endif /* NVGPU_PERF_TU104_H */

105
drivers/gpu/nvgpu/common/pmu/perf/pmu_perf.c
View File

@@ -28,108 +28,7 @@
#include "pmu_perf.h"
struct perfrpc_pmucmdhandler_params {
struct nv_pmu_perf_rpc *prpccall;
u32 success;
};
static void perfrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
void *param, u32 handle, u32 status)
{
struct perfrpc_pmucmdhandler_params *phandlerparams =
(struct perfrpc_pmucmdhandler_params *)param;
nvgpu_log_info(g, " ");
if (msg->msg.perf.msg_type != NV_PMU_PERF_MSG_ID_RPC) {
nvgpu_err(g, "unsupported msg for VFE LOAD RPC %x",
msg->msg.perf.msg_type);
return;
}
if (phandlerparams->prpccall->b_supported) {
phandlerparams->success = 1;
}
}
static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg)
{
struct nv_pmu_perf_msg *msg = (struct nv_pmu_perf_msg *)pmu_msg;
nvgpu_log_fn(g, " ");
switch (msg->msg_type) {
case NV_PMU_PERF_MSG_ID_VFE_CALLBACK:
nvgpu_clk_arb_schedule_vf_table_update(g);
break;
default:
WARN_ON(true);
break;
}
return 0;
}
int perf_pmu_vfe_load(struct gk20a *g)
{
struct pmu_cmd cmd;
struct pmu_payload payload;
int status;
u32 seqdesc;
struct nv_pmu_perf_rpc rpccall;
struct perfrpc_pmucmdhandler_params handler;
(void) memset(&payload, 0, sizeof(struct pmu_payload));
(void) memset(&rpccall, 0, sizeof(struct nv_pmu_perf_rpc));
(void) memset(&handler, 0,
sizeof(struct perfrpc_pmucmdhandler_params));
/*register call back for future VFE updates*/
g->ops.pmu_perf.handle_pmu_perf_event = pmu_handle_perf_event;
rpccall.function = NV_PMU_PERF_RPC_ID_VFE_LOAD;
rpccall.params.vfe_load.b_load = true;
cmd.hdr.unit_id = PMU_UNIT_PERF;
cmd.hdr.size = (u32)sizeof(struct nv_pmu_perf_cmd) +
(u32)sizeof(struct pmu_hdr);
cmd.cmd.perf.cmd_type = NV_PMU_PERF_CMD_ID_RPC;
payload.in.buf = (u8 *)&rpccall;
payload.in.size = (u32)sizeof(struct nv_pmu_perf_rpc);
payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
payload.in.offset = NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET;
payload.out.buf = (u8 *)&rpccall;
payload.out.size = (u32)sizeof(struct nv_pmu_perf_rpc);
payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
payload.out.offset = NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET;
handler.prpccall = &rpccall;
handler.success = 0;
status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload,
PMU_COMMAND_QUEUE_LPQ,
perfrpc_pmucmdhandler, (void *)&handler,
&seqdesc);
if (status != 0) {
nvgpu_err(g, "unable to post perf RPC cmd %x",
cmd.cmd.perf.cmd_type);
goto done;
}
pmu_wait_message_cond(&g->pmu,
gk20a_get_gr_idle_timeout(g),
&handler.success, 1);
if (handler.success == 0U) {
status = -EINVAL;
nvgpu_err(g, "rpc call to load VFE failed");
}
done:
return status;
}
int perf_pmu_init_pmupstate(struct gk20a *g)
int nvgpu_perf_pmu_init_pmupstate(struct gk20a *g)
{
/* If already allocated, do not re-allocate */
if (g->perf_pmu != NULL) {
@@ -151,7 +50,7 @@ static void vfe_thread_stop_cb(void *data)
nvgpu_cond_signal(cond);
}
void perf_pmu_free_pmupstate(struct gk20a *g)
void nvgpu_perf_pmu_free_pmupstate(struct gk20a *g)
{
if (nvgpu_thread_is_running(&g->perf_pmu->vfe_init.state_task)) {
nvgpu_thread_stop_graceful(&g->perf_pmu->vfe_init.state_task,

4
drivers/gpu/nvgpu/common/pmu/perf/vfe_equ.c
View File

@@ -75,7 +75,7 @@ static int vfe_equs_pmudata_instget(struct gk20a *g,
return 0;
}
int vfe_equ_sw_setup(struct gk20a *g)
int nvgpu_vfe_equ_sw_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
@@ -118,7 +118,7 @@ done:
return status;
}
int vfe_equ_pmu_setup(struct gk20a *g)
int nvgpu_vfe_equ_pmu_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;

4
drivers/gpu/nvgpu/common/pmu/perf/vfe_var.c
View File

@@ -182,7 +182,7 @@ int nvgpu_vfe_var_boardobj_grp_get_status(struct gk20a *g) {
return 0;
}
int vfe_var_sw_setup(struct gk20a *g)
int nvgpu_vfe_var_sw_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;
@@ -236,7 +236,7 @@ done:
return status;
}
int vfe_var_pmu_setup(struct gk20a *g)
int nvgpu_vfe_var_pmu_setup(struct gk20a *g)
{
int status;
struct boardobjgrp *pboardobjgrp = NULL;

4
drivers/gpu/nvgpu/common/pmu/perf/vfe_var.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -106,6 +106,4 @@ struct vfe_var_single_sensed_temp {
int temp_default;
};
int nvgpu_vfe_var_boardobj_grp_get_status(struct gk20a *g);
#endif /* NVGPU_PERF_VFE_VAR_H */

14
drivers/gpu/nvgpu/common/pmu/pstate/pstate.c
View File

@@ -38,7 +38,7 @@ void gk20a_deinit_pstate_support(struct gk20a *g)
{
pmgr_pmu_free_pmupstate(g);
nvgpu_therm_pmu_free_pmupstate(g);
perf_pmu_free_pmupstate(g);
nvgpu_perf_pmu_free_pmupstate(g);
nvgpu_clk_free_pmupstate(g);
if (g->ops.clk.mclk_deinit != NULL) {
@@ -64,7 +64,7 @@ int gk20a_init_pstate_support(struct gk20a *g)
return err;
}
err = perf_pmu_init_pmupstate(g);
err = nvgpu_perf_pmu_init_pmupstate(g);
if (err != 0) {
goto err_clk_init_pmupstate;
}
@@ -110,12 +110,12 @@ int gk20a_init_pstate_support(struct gk20a *g)
}
if (g->ops.pmu_perf.support_vfe) {
err = vfe_var_sw_setup(g);
err = nvgpu_vfe_var_sw_setup(g);
if (err != 0) {
goto err_pmgr_pmu_init_pmupstate;
}
err = vfe_equ_sw_setup(g);
err = nvgpu_vfe_equ_sw_setup(g);
if (err != 0) {
goto err_pmgr_pmu_init_pmupstate;
}
@@ -186,7 +186,7 @@ err_pmgr_pmu_init_pmupstate:
err_therm_pmu_init_pmupstate:
nvgpu_therm_pmu_free_pmupstate(g);
err_perf_pmu_init_pmupstate:
perf_pmu_free_pmupstate(g);
nvgpu_perf_pmu_free_pmupstate(g);
err_clk_init_pmupstate:
nvgpu_clk_free_pmupstate(g);
@@ -237,12 +237,12 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
}
if (g->ops.pmu_perf.support_vfe) {
err = vfe_var_pmu_setup(g);
err = nvgpu_vfe_var_pmu_setup(g);
if (err != 0) {
return err;
}
err = vfe_equ_pmu_setup(g);
err = nvgpu_vfe_equ_pmu_setup(g);
if (err != 0) {
return err;
}

16
drivers/gpu/nvgpu/include/nvgpu/pmu/perf.h
View File

@@ -90,15 +90,17 @@ struct perf_pmupstate {
struct change_seq_pmu changeseq_pmu;
};
int perf_pmu_vfe_load(struct gk20a *g);
int perf_pmu_init_pmupstate(struct gk20a *g);
void perf_pmu_free_pmupstate(struct gk20a *g);
int nvgpu_perf_pmu_init_pmupstate(struct gk20a *g);
void nvgpu_perf_pmu_free_pmupstate(struct gk20a *g);
int nvgpu_perf_pmu_vfe_load_ps35(struct gk20a *g);
int vfe_equ_sw_setup(struct gk20a *g);
int vfe_equ_pmu_setup(struct gk20a *g);
int nvgpu_vfe_equ_sw_setup(struct gk20a *g);
int nvgpu_vfe_equ_pmu_setup(struct gk20a *g);
int nvgpu_vfe_var_sw_setup(struct gk20a *g);
int nvgpu_vfe_var_pmu_setup(struct gk20a *g);
int nvgpu_vfe_var_boardobj_grp_get_status(struct gk20a *g);
int vfe_var_sw_setup(struct gk20a *g);
int vfe_var_pmu_setup(struct gk20a *g);
int nvgpu_vfe_get_volt_margin_limit(struct gk20a *g, u32 *vmargin_uv);
int nvgpu_vfe_get_freq_margin_limit(struct gk20a *g, u32 *fmargin_mhz);

6
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -70,7 +70,6 @@
#include "common/pmu/pmu_gv100.h"
#include "common/pmu/pmu_gv11b.h"
#include "common/pmu/pmu_tu104.h"
#include "common/pmu/perf/perf_tu104.h"
#include "common/acr/acr_tu104.h"
#include "common/falcon/falcon_gk20a.h"
#include "common/falcon/falcon_tu104.h"
@@ -155,6 +154,7 @@
#include <nvgpu/regops.h>
#include <nvgpu/gr/zbc.h>
#include <nvgpu/gr/fecs_trace.h>
#include <nvgpu/pmu/perf.h>
#include <nvgpu/hw/tu104/hw_proj_tu104.h>
#include <nvgpu/hw/tu104/hw_top_tu104.h>
@@ -970,7 +970,7 @@ static const struct gpu_ops tu104_ops = {
.get_rate_cntr = gv100_get_rate_cntr,
.measure_freq = gv100_clk_measure_freq,
.suspend_clk_support = gv100_suspend_clk_support,
.perf_pmu_vfe_load = tu104_perf_pmu_vfe_load,
.perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35,
.clk_domain_get_f_points = gv100_clk_domain_get_f_points,
},
.clk_arb = {
@@ -1284,7 +1284,7 @@ int tu104_init_hal(struct gk20a *g)
gops->pmu_perf.support_vfe = true;
gops->clk.support_vf_point = true;
gops->clk.lut_num_entries = CTRL_CLK_LUT_NUM_ENTRIES_GV10x;
gops->clk.perf_pmu_vfe_load = tu104_perf_pmu_vfe_load;
gops->clk.perf_pmu_vfe_load = nvgpu_perf_pmu_vfe_load_ps35;
/* dGpu VDK support */
if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)){