gpu: nvgpu: create nvgpu.common.hal.clk

Create unit nvgpu.common.hal.clk in by moving clk_*.[ch] files to
hal/clk path. Also update makefiles and include files to match.

JIRA NVGPU-2020

Change-Id: Ied217cfac2b000a2d22eda582d6030d0479b1310
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101400
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/hal/clk/clk_gk20a.h

@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2011 - 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef CLK_GK20A_H
+#define CLK_GK20A_H
+
+#include <nvgpu/lock.h>
+
+#if defined(CONFIG_COMMON_CLK)
+#include <linux/clk-provider.h>
+#endif
+
+#define GPUFREQ_TABLE_END     ~(u32)1
+enum gpc_pll_id {
+	/* only one PLL for gk20a */
+	GK20A_GPC_PLL = 0,
+	/* 2 PLL revisions for gm20b */
+	GM20B_GPC_PLL_B1,
+	GM20B_GPC_PLL_C1,
+};
+
+enum gpc_pll_mode {
+	GPC_PLL_MODE_F = 0,	/* fixed frequency mode a.k.a legacy mode */
+	GPC_PLL_MODE_DVFS,	/* DVFS mode a.k.a NA mode */
+};
+
+struct na_dvfs {
+	u32 n_int;
+	u32 sdm_din;
+	int dfs_coeff;
+	int dfs_det_max;
+	int dfs_ext_cal;
+	int uv_cal;
+	int mv;
+};
+
+struct pll {
+	enum gpc_pll_id id;
+	u32 clk_in;	/* KHz */
+	u32 M;
+	u32 N;
+	u32 PL;
+	u32 freq;	/* KHz */
+	bool enabled;
+	enum gpc_pll_mode mode;
+	struct na_dvfs dvfs;
+};
+
+struct pll_parms {
+	u32 min_freq, max_freq;	/* KHz */
+	u32 min_vco, max_vco;	/* KHz */
+	u32 min_u,   max_u;	/* KHz */
+	u32 min_M,   max_M;
+	u32 min_N,   max_N;
+	u32 min_PL,  max_PL;
+	/* NA mode parameters*/
+	int coeff_slope, coeff_offs; /* coeff = slope * V + offs */
+	int uvdet_slope, uvdet_offs; /* uV = slope * det + offs */
+	u32 vco_ctrl;
+	/*
+	 * Timing parameters in us. Lock timeout is applied to locking in fixed
+	 * frequency mode and to dynamic ramp in any mode; does not affect lock
+	 * latency, since lock/ramp done status bit is polled. NA mode lock and
+	 * and IDDQ exit delays set the time of the respective opertaions with
+	 * no status polling.
+	 */
+	u32 lock_timeout;
+	u32 na_lock_delay;
+	u32 iddq_exit_delay;
+	/* NA mode DFS control */
+	u32 dfs_ctrl;
+};
+
+struct namemap_cfg;
+
+struct clk_gk20a {
+	struct gk20a *g;
+#if defined(CONFIG_COMMON_CLK)
+	struct clk *tegra_clk;
+	struct clk_hw hw;
+
+	/* scaling rate */
+	unsigned long cached_rate;
+#endif
+	struct pll gpc_pll;
+	struct pll gpc_pll_last;
+	struct nvgpu_mutex clk_mutex;
+	struct namemap_cfg *clk_namemap;
+	u32 namemap_num;
+	u32 *namemap_xlat_table;
+	bool sw_ready;
+	bool clk_hw_on;
+	bool debugfs_set;
+	int pll_poweron_uv;
+	unsigned long dvfs_safe_max_freq;
+};
+
+struct gpu_ops;
+
+#define KHZ 1000U
+#define MHZ 1000000U
+
+static inline unsigned long rate_gpc2clk_to_gpu(unsigned long rate)
+{
+	/* convert the kHz gpc2clk frequency to Hz gpcpll frequency */
+	return (rate * KHZ) / 2U;
+}
+static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate)
+{
+	/* convert the Hz gpcpll frequency to kHz gpc2clk frequency */
+	return (rate * 2U) / KHZ;
+}
+
+#endif /* CLK_GK20A_H */

drivers/gpu/nvgpu/hal/clk/clk_gm20b.h

@@ -0,0 +1,93 @@
+/*
+ * GM20B Graphics
+ *
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef NVGPU_GM20B_CLK_GM20B_H
+#define NVGPU_GM20B_CLK_GM20B_H
+
+#include <nvgpu/lock.h>
+
+struct gk20a;
+struct clk_gk20a;
+
+struct nvgpu_clk_pll_debug_data {
+	u32 trim_sys_sel_vco_reg;
+	u32 trim_sys_sel_vco_val;
+
+	u32 trim_sys_gpc2clk_out_reg;
+	u32 trim_sys_gpc2clk_out_val;
+
+	u32 trim_sys_bypassctrl_reg;
+	u32 trim_sys_bypassctrl_val;
+
+	u32 trim_sys_gpcpll_cfg_reg;
+	u32 trim_sys_gpcpll_dvfs2_reg;
+	u32 trim_bcast_gpcpll_dvfs2_reg;
+
+	u32 trim_sys_gpcpll_cfg_val;
+	bool trim_sys_gpcpll_cfg_enabled;
+	bool trim_sys_gpcpll_cfg_locked;
+	bool trim_sys_gpcpll_cfg_sync_on;
+
+	u32 trim_sys_gpcpll_coeff_val;
+	u32 trim_sys_gpcpll_coeff_mdiv;
+	u32 trim_sys_gpcpll_coeff_ndiv;
+	u32 trim_sys_gpcpll_coeff_pldiv;
+
+	u32 trim_sys_gpcpll_dvfs0_val;
+	u32 trim_sys_gpcpll_dvfs0_dfs_coeff;
+	u32 trim_sys_gpcpll_dvfs0_dfs_det_max;
+	u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset;
+};
+
+int gm20b_init_clk_setup_sw(struct gk20a *g);
+
+int gm20b_clk_prepare(struct clk_gk20a *clk);
+void gm20b_clk_unprepare(struct clk_gk20a *clk);
+int gm20b_clk_is_prepared(struct clk_gk20a *clk);
+unsigned long gm20b_recalc_rate(struct clk_gk20a *clk, unsigned long parent_rate);
+int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate,
+		unsigned long parent_rate);
+long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate,
+		unsigned long *parent_rate);
+struct pll_parms *gm20b_get_gpc_pll_parms(void);
+
+int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val);
+int gm20b_init_clk_support(struct gk20a *g);
+void gm20b_suspend_clk_support(struct gk20a *g);
+int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val);
+int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val);
+int gm20b_clk_get_pll_debug_data(struct gk20a *g,
+			struct nvgpu_clk_pll_debug_data *d);
+
+/* 1:1 match between post divider settings and divisor value */
+static inline u32 nvgpu_pl_to_div(u32 pl)
+{
+	return pl;
+}
+
+static inline u32 nvgpu_div_to_pl(u32 divisor)
+{
+	return divisor;
+}
+
+#endif /* NVGPU_GM20B_CLK_GM20B_H */

drivers/gpu/nvgpu/hal/clk/clk_gv100.c

@@ -0,0 +1,240 @@
+/*
+ * GV100 Clocks
+ *
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include "os/linux/os_linux.h"
+#endif
+
+#include <nvgpu/kmem.h>
+#include <nvgpu/io.h>
+#include <nvgpu/list.h>
+#include <nvgpu/clk_arb.h>
+#include <nvgpu/timers.h>
+#include <nvgpu/gk20a.h>
+#include <nvgpu/clk.h>
+#include <nvgpu/pmu/clk/clk.h>
+#include <nvgpu/pmu/clk/clk_domain.h>
+#include <nvgpu/hw/gv100/hw_trim_gv100.h>
+
+#include "clk_gv100.h"
+
+
+
+#define CLK_NAMEMAP_INDEX_GPCCLK	0x00
+#define CLK_NAMEMAP_INDEX_XBARCLK	0x02
+#define CLK_NAMEMAP_INDEX_SYSCLK	0x07	/* SYSPLL */
+#define CLK_NAMEMAP_INDEX_DRAMCLK	0x20	/* DRAMPLL */
+
+#define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10
+#define CLK_DEFAULT_CNTRL_SETTLE_USECS   5
+
+#define XTAL_CNTR_CLKS		27000	/* 1000usec at 27KHz XTAL */
+#define XTAL_CNTR_DELAY		10000	/* we need acuracy up to the 10ms   */
+#define XTAL_SCALE_TO_KHZ	1
+#define NUM_NAMEMAPS    (3U)
+#define XTAL4X_KHZ 108000
+
+u32 gv100_crystal_clk_hz(struct gk20a *g)
+{
+	return (XTAL4X_KHZ * 1000);
+}
+
+unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain)
+{
+	struct clk_gk20a *clk = &g->clk;
+	u32 freq_khz;
+	u32 i;
+	struct namemap_cfg *c = NULL;
+
+	for (i = 0; i < clk->namemap_num; i++) {
+		if (api_domain == clk->namemap_xlat_table[i]) {
+			c = &clk->clk_namemap[i];
+			break;
+		}
+	}
+
+	if (c == NULL) {
+		return 0;
+	}
+	if (c->is_counter != 0U) {
+		freq_khz = c->scale * gv100_get_rate_cntr(g, c);
+	} else {
+		freq_khz = 0U;
+		 /* TODO: PLL read */
+	}
+
+	/* Convert to HZ */
+	return (freq_khz * 1000UL);
+}
+
+int gv100_init_clk_support(struct gk20a *g)
+{
+	struct clk_gk20a *clk = &g->clk;
+	int err = 0;
+
+	nvgpu_log_fn(g, " ");
+
+	err = nvgpu_mutex_init(&clk->clk_mutex);
+	if (err != 0) {
+		return err;
+	}
+
+	clk->clk_namemap = (struct namemap_cfg *)
+		nvgpu_kzalloc(g, sizeof(struct namemap_cfg) * NUM_NAMEMAPS);
+
+	if (clk->clk_namemap == NULL) {
+		nvgpu_mutex_destroy(&clk->clk_mutex);
+		return -ENOMEM;
+	}
+
+	clk->namemap_xlat_table = nvgpu_kcalloc(g, NUM_NAMEMAPS, sizeof(u32));
+
+	if (clk->namemap_xlat_table == NULL) {
+		nvgpu_kfree(g, clk->clk_namemap);
+		nvgpu_mutex_destroy(&clk->clk_mutex);
+		return -ENOMEM;
+	}
+
+	clk->clk_namemap[0] = (struct namemap_cfg) {
+		.namemap = CLK_NAMEMAP_INDEX_GPCCLK,
+		.is_enable = 1,
+		.is_counter = 1,
+		.g = g,
+		.cntr = {
+			.reg_ctrl_addr = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(),
+			.reg_ctrl_idx  = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_f(),
+			.reg_cntr_addr[0] = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r(),
+			.reg_cntr_addr[1] = trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r()
+		},
+		.name = "gpcclk",
+		.scale = 1
+	};
+	clk->namemap_xlat_table[0] = CTRL_CLK_DOMAIN_GPCCLK;
+
+	clk->clk_namemap[1] = (struct namemap_cfg) {
+		.namemap = CLK_NAMEMAP_INDEX_SYSCLK,
+		.is_enable = 1,
+		.is_counter = 1,
+		.g = g,
+		.cntr = {
+			.reg_ctrl_addr = trim_sys_fr_clk_cntr_sysclk_cfg_r(),
+			.reg_ctrl_idx  = trim_sys_fr_clk_cntr_sysclk_cfg_source_sysclk_f(),
+			.reg_cntr_addr[0] = trim_sys_fr_clk_cntr_sysclk_cntr0_r(),
+			.reg_cntr_addr[1] = trim_sys_fr_clk_cntr_sysclk_cntr1_r()
+		},
+		.name = "sysclk",
+		.scale = 1
+	};
+	clk->namemap_xlat_table[1] = CTRL_CLK_DOMAIN_SYSCLK;
+
+	clk->clk_namemap[2] = (struct namemap_cfg) {
+		.namemap = CLK_NAMEMAP_INDEX_XBARCLK,
+		.is_enable = 1,
+		.is_counter = 1,
+		.g = g,
+		.cntr = {
+			.reg_ctrl_addr = trim_sys_fll_fr_clk_cntr_xbarclk_cfg_r(),
+			.reg_ctrl_idx  = trim_sys_fll_fr_clk_cntr_xbarclk_cfg_source_xbarclk_f(),
+			.reg_cntr_addr[0] = trim_sys_fll_fr_clk_cntr_xbarclk_cntr0_r(),
+			.reg_cntr_addr[1] = trim_sys_fll_fr_clk_cntr_xbarclk_cntr1_r()
+		},
+		.name = "xbarclk",
+		.scale = 1
+	};
+	clk->namemap_xlat_table[2] = CTRL_CLK_DOMAIN_XBARCLK;
+
+	clk->namemap_num = NUM_NAMEMAPS;
+
+	clk->g = g;
+
+	return err;
+}
+
+u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
+	u32 cntr = 0;
+	u64 cntr_start = 0;
+	u64 cntr_stop = 0;
+	u64 start_time, stop_time;
+
+	struct clk_gk20a *clk = &g->clk;
+
+	if ((c == NULL) || (c->cntr.reg_ctrl_addr == 0U) ||
+		(c->cntr.reg_cntr_addr[0] == 0U) ||
+		(c->cntr.reg_cntr_addr[1]) == 0U) {
+			return 0;
+	}
+
+	nvgpu_mutex_acquire(&clk->clk_mutex);
+
+	/* Read the counter values */
+	/* Counter is 36bits , 32 bits on addr[0] and 4 lsb on addr[1] others zero*/
+	cntr_start = (u64)gk20a_readl(g, c->cntr.reg_cntr_addr[0]);
+	cntr_start += ((u64)gk20a_readl(g, c->cntr.reg_cntr_addr[1]) << 32);
+	start_time = (u64)nvgpu_current_time_ms();
+	nvgpu_udelay(XTAL_CNTR_DELAY);
+	stop_time = (u64)nvgpu_current_time_ms();
+	cntr_stop = (u64)gk20a_readl(g, c->cntr.reg_cntr_addr[0]);
+	cntr_stop += ((u64)gk20a_readl(g, c->cntr.reg_cntr_addr[1]) << 32);
+	/*Calculate the difference with Acutal time and convert to KHz*/
+	cntr = ((u32)(cntr_stop - cntr_start) / (u32)(stop_time-start_time));
+	nvgpu_mutex_release(&clk->clk_mutex);
+
+	return cntr;
+
+}
+
+int gv100_clk_domain_get_f_points(
+	struct gk20a *g,
+	u32 clkapidomain,
+	u32 *pfpointscount,
+	u16 *pfreqpointsinmhz)
+{
+	int status = -EINVAL;
+	struct nvgpu_clk_domain *pdomain;
+	u8 i;
+	struct nvgpu_clk_pmupstate *pclk = g->clk_pmu;
+	if (pfpointscount == NULL) {
+		return -EINVAL;
+	}
+
+	if ((pfreqpointsinmhz == NULL) && (*pfpointscount != 0U)) {
+		return -EINVAL;
+	}
+	BOARDOBJGRP_FOR_EACH(&(pclk->clk_domainobjs->super.super),
+			struct nvgpu_clk_domain *, pdomain, i) {
+		if (pdomain->api_domain == clkapidomain) {
+			status = pdomain->clkdomainclkgetfpoints(g, pclk,
+				pdomain, pfpointscount,
+				pfreqpointsinmhz,
+				CLK_PROG_VFE_ENTRY_LOGIC);
+			return status;
+		}
+	}
+	return status;
+}
+void gv100_suspend_clk_support(struct gk20a *g)
+{
+	nvgpu_mutex_destroy(&g->clk.clk_mutex);
+}

drivers/gpu/nvgpu/hal/clk/clk_gv100.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+#ifndef CLK_GV100_H
+#define CLK_GV100_H
+
+#include <nvgpu/lock.h>
+#include <nvgpu/gk20a.h>
+
+u32 gv100_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
+int gv100_init_clk_support(struct gk20a *g);
+u32 gv100_crystal_clk_hz(struct gk20a *g);
+unsigned long gv100_clk_measure_freq(struct gk20a *g, u32 api_domain);
+void gv100_suspend_clk_support(struct gk20a *g);
+int gv100_clk_domain_get_f_points(
+	struct gk20a *g,
+	u32 clkapidomain,
+	u32 *pfpointscount,
+	u16 *pfreqpointsinmhz);
+#endif /* CLK_GV100_H */

drivers/gpu/nvgpu/hal/init/hal_gm20b.c

@@ -85,6 +85,7 @@
 #include "hal/falcon/falcon_gk20a.h"
 #include "hal/perf/perf_gm20b.h"
 #include "hal/netlist/netlist_gm20b.h"
+#include "hal/clk/clk_gm20b.h"
 
 #include "common/top/top_gm20b.h"
 #include "common/sync/syncpt_cmdbuf_gk20a.h"
@@ -95,7 +96,6 @@
 
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/mm_gm20b.h"
-#include "gm20b/clk_gm20b.h"
 #include "hal_gm20b.h"
 
 #include <nvgpu/hw/gm20b/hw_proj_gm20b.h>

drivers/gpu/nvgpu/hal/init/hal_gv100.c

@@ -148,7 +148,7 @@
 #include "gv100/fifo_gv100.h"
 #include "gv100/gr_gv100.h"
 #include "gv100/mm_gv100.h"
-#include "gv100/clk_gv100.h"
+#include "hal/clk/clk_gv100.h"
 
 #include <nvgpu/ptimer.h>
 #include <nvgpu/class.h>

drivers/gpu/nvgpu/hal/init/hal_tu104.c

@@ -147,7 +147,7 @@
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/mm_gm20b.h"
 
-#include "gv100/clk_gv100.h"
+#include "hal/clk/clk_gv100.h"
 
 
 #include "gp10b/gr_gp10b.h"