gpu: nvgpu: enable ce2 interrupts

enables non-blocking interrupts in ce2 all other
ce2 interrupts are cleared and not handled.

bug 200036089

Change-Id: I9f47b06c677c72ac523019e6a3f70fedd07830a2
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/671783
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -19,6 +19,7 @@ nvgpu-y := \
 	gk20a/gk20a.o \
 	gk20a/as_gk20a.o \
 	gk20a/ctrl_gk20a.o \
+	gk20a/ce2_gk20a.o \
 	gk20a/fifo_gk20a.o \
 	gk20a/channel_gk20a.o \
 	gk20a/channel_sync_gk20a.o \

drivers/gpu/nvgpu/gk20a/ce2_gk20a.c

@@ -0,0 +1,95 @@
+/*
+ * GK20A Graphics Copy Engine  (gr host)
+ *
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*TODO: remove uncecessary */
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/scatterlist.h>
+#include <trace/events/gk20a.h>
+#include <linux/dma-mapping.h>
+#include <linux/nvhost.h>
+
+#include "gk20a.h"
+#include "debug_gk20a.h"
+#include "semaphore_gk20a.h"
+#include "hw_ce2_gk20a.h"
+#include "hw_pbdma_gk20a.h"
+#include "hw_ccsr_gk20a.h"
+#include "hw_ram_gk20a.h"
+#include "hw_proj_gk20a.h"
+#include "hw_top_gk20a.h"
+#include "hw_mc_gk20a.h"
+#include "hw_gr_gk20a.h"
+
+static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr)
+{
+	gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n");
+
+	/* wake theads waiting in this channel */
+	gk20a_channel_semaphore_wakeup(g);
+	return ce2_intr_status_nonblockpipe_pending_f();
+}
+
+static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr)
+{
+	gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n");
+
+	return ce2_intr_status_blockpipe_pending_f();
+}
+
+static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr)
+{
+	gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n");
+
+	return ce2_intr_status_launcherr_pending_f();
+}
+
+void gk20a_ce2_isr(struct gk20a *g)
+{
+	u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
+	u32 clear_intr = 0;
+
+	gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr);
+
+	/* clear blocking interrupts: they exibit broken behavior */
+	if (ce2_intr & ce2_intr_status_blockpipe_pending_f())
+		clear_intr |= ce2_blockpipe_isr(g, ce2_intr);
+
+	if (ce2_intr & ce2_intr_status_launcherr_pending_f())
+		clear_intr |= ce2_launcherr_isr(g, ce2_intr);
+
+	gk20a_writel(g, ce2_intr_status_r(), clear_intr);
+	return;
+}
+
+void gk20a_ce2_nonstall_isr(struct gk20a *g)
+{
+	u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r());
+	u32 clear_intr = 0;
+
+	gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr);
+
+	if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f())
+		clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr);
+
+	gk20a_writel(g, ce2_intr_status_r(), clear_intr);
+
+	return;
+}
+

drivers/gpu/nvgpu/gk20a/ce2_gk20a.h

@@ -0,0 +1,30 @@
+/*
+ * drivers/video/tegra/host/gk20a/fifo_gk20a.h
+ *
+ * GK20A graphics copy engine (gr host)
+ *
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __CE2_GK20A_H__
+#define __CE2_GK20A_H__
+
+#include "channel_gk20a.h"
+#include "tsg_gk20a.h"
+
+void gk20a_ce2_isr(struct gk20a *g);
+void gk20a_ce2_nonstall_isr(struct gk20a *g);
+
+#endif /*__CE2_GK20A_H__*/

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -37,6 +37,7 @@ struct acr_gm20b;
 
 #include "as_gk20a.h"
 #include "clk_gk20a.h"
+#include "ce2_gk20a.h"
 #include "fifo_gk20a.h"
 #include "tsg_gk20a.h"
 #include "gr_gk20a.h"

drivers/gpu/nvgpu/gk20a/hw_ce2_gk20a.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce2_gk20a_h_
+#define _hw_ce2_gk20a_h_
+
+static inline u32 ce2_intr_status_r(void)
+{
+	return 0x00106908;
+}
+static inline u32 ce2_intr_status_blockpipe_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ce2_intr_status_blockpipe_reset_f(void)
+{
+	return 0x1;
+}
+static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
+{
+	return 0x2;
+}
+static inline u32 ce2_intr_status_launcherr_pending_f(void)
+{
+	return 0x4;
+}
+static inline u32 ce2_intr_status_launcherr_reset_f(void)
+{
+	return 0x4;
+}
+#endif

drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -1302,6 +1302,10 @@ static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
 {
 	return (v & 0xffffffff) << 0;
 }
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+	return 0x00000028;
+}
 static inline u32 gr_ds_zbc_color_g_r(void)
 {
 	return 0x00405808;
@@ -1350,10 +1354,6 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
 {
 	return 0x00000004;
 }
-static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
-{
-	return 0x00000028;
-}
 static inline u32 gr_ds_zbc_z_r(void)
 {
 	return 0x00405818;

drivers/gpu/nvgpu/gk20a/hw_mc_gk20a.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2012-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,

drivers/gpu/nvgpu/gk20a/mc_gk20a.c

@@ -1,7 +1,7 @@
 /*
  * GK20A memory interface
  *
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -73,6 +73,8 @@ irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g)
 
 	if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
 		gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g));
+	if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id))
+		gk20a_ce2_isr(g);
 	if (mc_intr_0 & mc_intr_0_pfifo_pending_f())
 		gk20a_fifo_isr(g);
 	if (mc_intr_0 & mc_intr_0_pmu_pending_f())
@@ -107,6 +109,8 @@ irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g)
 		gk20a_fifo_nonstall_isr(g);
 	if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id))
 		gk20a_gr_nonstall_isr(g);
+	if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id))
+		gk20a_ce2_nonstall_isr(g);
 
 	gk20a_writel(g, mc_intr_en_1_r(),
 		mc_intr_en_1_inta_hardware_f());

drivers/gpu/nvgpu/gm20b/hw_ce2_gm20b.h

@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce2_gm20b_h_
+#define _hw_ce2_gm20b_h_
+
+static inline u32 ce2_intr_status_r(void)
+{
+	return 0x00106908;
+}
+static inline u32 ce2_intr_status_blockpipe_pending_f(void)
+{
+	return 0x1;
+}
+static inline u32 ce2_intr_status_blockpipe_reset_f(void)
+{
+	return 0x1;
+}
+static inline u32 ce2_intr_status_nonblockpipe_pending_f(void)
+{
+	return 0x2;
+}
+static inline u32 ce2_intr_status_nonblockpipe_reset_f(void)
+{
+	return 0x2;
+}
+static inline u32 ce2_intr_status_launcherr_pending_f(void)
+{
+	return 0x4;
+}
+static inline u32 ce2_intr_status_launcherr_reset_f(void)
+{
+	return 0x4;
+}
+#endif

drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -1302,10 +1302,6 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
 {
 	return 0x00000004;
 }
-static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
-{
-	return 0x00000028;
-}
 static inline u32 gr_ds_zbc_z_r(void)
 {
 	return 0x00405818;

drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,