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gpu: nvgpu: add multi gr handling for debugger

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Added multi gr handling for debugger apis.
Replaced g->gr with nvgpu_gr_get_cur_instance_ptr(g).

JIRA NVGPU-5656

Change-Id: I010eff39b1ebec231b4dbdd53caffc25e1cd54c4
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2537784
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Lakshmanan M
2021-06-01 14:44:25 +05:30
committed by mobile promotions
parent 11d27743f8
commit edbcf5cfc6
4 changed files with 86 additions and 65 deletions
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45
drivers/gpu/nvgpu/hal/gr/gr/gr_gk20a.c
View File

@@ -39,6 +39,7 @@
#include <nvgpu/gr/subctx.h>
#include <nvgpu/gr/ctx.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_instances.h>
#include <nvgpu/gr/gr_intr.h>
#include <nvgpu/gr/obj_ctx.h>
#include <nvgpu/gr/config.h>
@@ -85,18 +86,19 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
bool skip_update = false;
int err;
int ret;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
nvgpu_log_fn(g, " ");
gr_ctx = tsg->gr_ctx;
if (mode != NVGPU_GR_CTX_HWPM_CTXSW_MODE_NO_CTXSW) {
nvgpu_gr_ctx_set_size(g->gr->gr_ctx_desc,
nvgpu_gr_ctx_set_size(gr->gr_ctx_desc,
NVGPU_GR_CTX_PM_CTX,
nvgpu_gr_hwpm_map_get_size(g->gr->hwpm_map));
nvgpu_gr_hwpm_map_get_size(gr->hwpm_map));
ret = nvgpu_gr_ctx_alloc_pm_ctx(g, gr_ctx,
g->gr->gr_ctx_desc, tsg->vm,
gr->gr_ctx_desc, tsg->vm,
gpu_va);
if (ret != 0) {
nvgpu_err(g,
@@ -287,11 +289,12 @@ int gr_gk20a_split_ppc_broadcast_addr(struct gk20a *g, u32 addr,
u32 *priv_addr_table, u32 *t)
{
u32 ppc_num;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "addr=0x%x", addr);
for (ppc_num = 0;
ppc_num < nvgpu_gr_config_get_gpc_ppc_count(g->gr->config, gpc_num);
ppc_num < nvgpu_gr_config_get_gpc_ppc_count(gr->config, gpc_num);
ppc_num++) {
priv_addr_table[(*t)++] = pri_ppc_addr(g, pri_ppccs_addr_mask(addr),
gpc_num, ppc_num);
@@ -318,7 +321,8 @@ int gr_gk20a_create_priv_addr_table(struct gk20a *g,
u32 broadcast_flags;
u32 t;
int err;
struct nvgpu_gr_config *gr_config = g->gr->config;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
struct nvgpu_gr_config *gr_config = gr->config;
t = 0;
*num_registers = 0;
@@ -438,7 +442,7 @@ int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g,
u32 *priv_registers;
u32 num_registers = 0;
int err = 0;
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
u32 potential_offsets = nvgpu_gr_config_get_max_gpc_count(gr->config) *
nvgpu_gr_config_get_max_tpc_per_gpc_count(gr->config) *
@@ -485,9 +489,9 @@ int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g,
err = g->ops.gr.find_priv_offset_in_buffer(g,
priv_registers[i],
nvgpu_gr_obj_ctx_get_local_golden_image_ptr(
g->gr->golden_image),
gr->golden_image),
nvgpu_gr_obj_ctx_get_golden_image_size(
g->gr->golden_image),
gr->golden_image),
&priv_offset);
if (err != 0) {
nvgpu_log_fn(g, "Could not determine priv_offset for addr:0x%x",
@@ -519,7 +523,7 @@ int gr_gk20a_get_pm_ctx_buffer_offsets(struct gk20a *g,
u32 *priv_registers;
u32 num_registers = 0;
int err = 0;
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
u32 potential_offsets = nvgpu_gr_config_get_max_gpc_count(gr->config) *
nvgpu_gr_config_get_max_tpc_per_gpc_count(gr->config) *
@@ -559,7 +563,7 @@ int gr_gk20a_get_pm_ctx_buffer_offsets(struct gk20a *g,
}
for (i = 0; i < num_registers; i++) {
err = nvgpu_gr_hwmp_map_find_priv_offset(g, g->gr->hwpm_map,
err = nvgpu_gr_hwmp_map_find_priv_offset(g, gr->hwpm_map,
priv_registers[i],
&priv_offset, gr->config);
if (err != 0) {
@@ -624,7 +628,8 @@ int gr_gk20a_ctx_patch_smpc(struct gk20a *g,
u32 addr, u32 data,
struct nvgpu_gr_ctx *gr_ctx)
{
u32 num_gpc = nvgpu_gr_config_get_gpc_count(g->gr->config);
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 num_gpc = nvgpu_gr_config_get_gpc_count(gr->config);
u32 num_tpc;
u32 tpc, gpc, reg;
u32 chk_addr;
@@ -641,7 +646,7 @@ int gr_gk20a_ctx_patch_smpc(struct gk20a *g,
for (reg = 0; reg < num_ovr_perf_regs; reg++) {
for (gpc = 0; gpc < num_gpc; gpc++) {
num_tpc = nvgpu_gr_config_get_gpc_tpc_count(g->gr->config, gpc);
num_tpc = nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc);
for (tpc = 0; tpc < num_tpc; tpc++) {
chk_addr = ((gpc_stride * gpc) +
(tpc_in_gpc_stride * tpc) +
@@ -705,7 +710,7 @@ int gr_gk20a_find_priv_offset_in_ext_buffer(struct gk20a *g,
u32 marker_size = 0;
u32 control_register_stride = 0;
u32 perf_register_stride = 0;
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE);
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
u32 tpc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_BASE);
@@ -1379,7 +1384,7 @@ static int gr_exec_ctx_ops(struct nvgpu_tsg *tsg,
bool pm_ctx_ready = false;
struct nvgpu_mem *current_mem = NULL;
u32 i, j, offset, v;
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
u32 max_offsets = nvgpu_gr_config_get_max_gpc_count(gr->config) *
nvgpu_gr_config_get_max_tpc_per_gpc_count(gr->config) *
@@ -1555,7 +1560,7 @@ static int gr_exec_ctx_ops(struct nvgpu_tsg *tsg,
if ((current_mem == nvgpu_gr_ctx_get_ctx_mem(gr_ctx)) &&
(offsets[j] >=
nvgpu_gr_obj_ctx_get_golden_image_size(
g->gr->golden_image))) {
gr->golden_image))) {
continue;
}
if (pass == 0) { /* write pass */
@@ -1782,7 +1787,7 @@ void gk20a_gr_suspend_single_sm(struct gk20a *g,
void gk20a_gr_suspend_all_sms(struct gk20a *g,
u32 global_esr_mask, bool check_errors)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc, tpc, sm;
int err;
u32 dbgr_control0;
@@ -1899,6 +1904,7 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
u32 no_of_sm = g->ops.gr.init.get_no_of_sm(g);
struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch);
u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
if (tsg == NULL) {
return -EINVAL;
@@ -1917,7 +1923,7 @@ int gr_gk20a_set_sm_debug_mode(struct gk20a *g,
if ((sms & BIT64(sm_id)) == 0ULL) {
continue;
}
sm_info = nvgpu_gr_config_get_sm_info(g->gr->config, sm_id);
sm_info = nvgpu_gr_config_get_sm_info(gr->config, sm_id);
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
@@ -2115,6 +2121,7 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state)
u32 gpc, tpc, sm, sm_id;
u32 global_mask;
u32 no_of_sm;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
if((g->ops.gr.init.get_no_of_sm == NULL) ||
(g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask == NULL) ||
@@ -2142,7 +2149,7 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state)
/* Lock down all SMs */
for (sm_id = 0; sm_id < no_of_sm; sm_id++) {
struct nvgpu_sm_info *sm_info =
nvgpu_gr_config_get_sm_info(g->gr->config, sm_id);
nvgpu_gr_config_get_sm_info(gr->config, sm_id);
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
sm = nvgpu_gr_config_get_sm_info_sm_index(sm_info);
@@ -2189,7 +2196,7 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g)
{
int ret = 0;
u32 gpc, tpc, sm;
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 global_esr;
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);

20
drivers/gpu/nvgpu/hal/gr/gr/gr_gm20b.c
View File

@@ -1,7 +1,7 @@
/*
* GM20B GPC MMU
*
* Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -35,6 +35,7 @@
#include <nvgpu/gr/ctx.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_instances.h>
#include <nvgpu/gr/warpstate.h>
#include <nvgpu/engines.h>
#include <nvgpu/engine_status.h>
@@ -54,7 +55,7 @@ u32 gr_gm20b_get_gr_status(struct gk20a *g)
void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc_index, ppc_index, stride, val;
u32 pd_ab_max_output;
u32 alpha_cb_size = data * 4U;
@@ -111,7 +112,7 @@ void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc_index, ppc_index, stride, val;
u32 cb_size = data * 4U;
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -217,13 +218,15 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
#ifdef CONFIG_NVGPU_TEGRA_FUSE
void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
{
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
nvgpu_tegra_fuse_write_bypass(g, 0x1);
nvgpu_tegra_fuse_write_access_sw(g, 0x0);
if (nvgpu_gr_config_get_gpc_tpc_mask(g->gr->config, gpc_index) == 0x1U) {
if (nvgpu_gr_config_get_gpc_tpc_mask(gr->config, gpc_index) == 0x1U) {
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0);
nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(g, 0x1);
} else if (nvgpu_gr_config_get_gpc_tpc_mask(g->gr->config, gpc_index) ==
} else if (nvgpu_gr_config_get_gpc_tpc_mask(gr->config, gpc_index) ==
0x2U) {
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1);
nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(g, 0x0);
@@ -237,7 +240,7 @@ void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
struct nvgpu_debug_context *o)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gr_engine_id;
struct nvgpu_engine_status_info engine_status;
@@ -423,7 +426,7 @@ void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
{
/* Check if we have at least one valid warp */
/* get paused state on maxwell */
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc, tpc, sm_id;
u32 tpc_offset, gpc_offset, reg_offset;
u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0;
@@ -511,6 +514,7 @@ int gm20b_gr_clear_sm_error_state(struct gk20a *g,
u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g,
GPU_LIT_TPC_IN_GPC_STRIDE);
int err = 0;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
tsg = nvgpu_tsg_from_ch(ch);
if (tsg == NULL) {
@@ -530,7 +534,7 @@ int gm20b_gr_clear_sm_error_state(struct gk20a *g,
if (gk20a_is_channel_ctx_resident(ch)) {
struct nvgpu_sm_info *sm_info =
nvgpu_gr_config_get_sm_info(g->gr->config, sm_id);
nvgpu_gr_config_get_sm_info(gr->config, sm_id);
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);

17
drivers/gpu/nvgpu/hal/gr/gr/gr_gp10b.c
View File

@@ -1,7 +1,7 @@
/*
* GP10B GPU GR
*
* Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2015-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -38,6 +38,7 @@
#include <nvgpu/gr/subctx.h>
#include <nvgpu/gr/ctx.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_instances.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/obj_ctx.h>
@@ -103,7 +104,7 @@ void gr_gp10b_set_bes_crop_debug4(struct gk20a *g, u32 data)
void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc_index, ppc_index, stride, val;
u32 pd_ab_max_output;
u32 alpha_cb_size = data * 4U;
@@ -158,7 +159,7 @@ void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc_index, ppc_index, stride, val;
u32 cb_size_steady = data * 4U, cb_size;
u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -234,7 +235,7 @@ void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data)
int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
struct nvgpu_debug_context *o)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gr_engine_id;
struct nvgpu_engine_status_info engine_status;
@@ -369,12 +370,13 @@ int gr_gp10b_dump_gr_status_regs(struct gk20a *g,
#ifdef CONFIG_NVGPU_TEGRA_FUSE
void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
{
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
nvgpu_tegra_fuse_write_bypass(g, 0x1);
nvgpu_tegra_fuse_write_access_sw(g, 0x0);
if (nvgpu_gr_config_get_gpc_tpc_mask(g->gr->config, gpc_index) == 0x1U) {
if (nvgpu_gr_config_get_gpc_tpc_mask(gr->config, gpc_index) == 0x1U) {
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2);
} else if (nvgpu_gr_config_get_gpc_tpc_mask(g->gr->config, gpc_index) ==
} else if (nvgpu_gr_config_get_gpc_tpc_mask(gr->config, gpc_index) ==
0x2U) {
nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1);
} else {
@@ -427,6 +429,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
int ret;
struct nvgpu_tsg *tsg;
struct nvgpu_gr_ctx *gr_ctx;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " ");
@@ -472,7 +475,7 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
/* set cilp_preempt_pending = true and record the channel */
nvgpu_gr_ctx_set_cilp_preempt_pending(gr_ctx, true);
g->gr->cilp_preempt_pending_chid = fault_ch->chid;
gr->cilp_preempt_pending_chid = fault_ch->chid;
#ifdef CONFIG_NVGPU_CHANNEL_TSG_CONTROL
g->ops.tsg.post_event_id(tsg, NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED);

69
drivers/gpu/nvgpu/hal/gr/gr/gr_gv11b.c
View File

@@ -37,6 +37,7 @@
#include <nvgpu/gr/ctx.h>
#include <nvgpu/gr/config.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/gr_instances.h>
#include <nvgpu/gr/warpstate.h>
#include <nvgpu/channel.h>
#include <nvgpu/engines.h>
@@ -63,7 +64,7 @@
void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc_index, ppc_index, stride, val;
u32 pd_ab_max_output;
u32 alpha_cb_size = data * 4U;
@@ -115,7 +116,7 @@ void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc_index, ppc_index, stride, val;
u32 cb_size_steady = data * 4U, cb_size;
u32 attrib_cb_size = g->ops.gr.init.get_attrib_cb_size(g,
@@ -226,6 +227,7 @@ static void gr_gv11b_dump_gr_sm_regs(struct gk20a *g,
{
u32 gpc, tpc, sm, sm_per_tpc;
u32 gpc_offset, tpc_offset, offset;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
gk20a_debug_output(o,
"NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK: 0x%x",
@@ -251,11 +253,11 @@ static void gr_gv11b_dump_gr_sm_regs(struct gk20a *g,
gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r()));
sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
for (gpc = 0; gpc < nvgpu_gr_config_get_gpc_count(g->gr->config); gpc++) {
for (gpc = 0; gpc < nvgpu_gr_config_get_gpc_count(gr->config); gpc++) {
gpc_offset = nvgpu_gr_gpc_offset(g, gpc);
for (tpc = 0;
tpc < nvgpu_gr_config_get_gpc_tpc_count(g->gr->config, gpc);
tpc < nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc);
tpc++) {
tpc_offset = nvgpu_gr_tpc_offset(g, tpc);
@@ -273,7 +275,7 @@ static void gr_gv11b_dump_gr_sm_regs(struct gk20a *g,
int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
struct nvgpu_debug_context *o)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gr_engine_id;
struct nvgpu_engine_status_info engine_status;
@@ -416,19 +418,20 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
{
u32 fuse_val;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
if (nvgpu_gr_config_get_gpc_tpc_mask(g->gr->config, gpc_index) == 0U) {
if (nvgpu_gr_config_get_gpc_tpc_mask(gr->config, gpc_index) == 0U) {
return;
}
/*
* For s/w value nvgpu_gr_config_get_gpc_tpc_mask(g->gr->config, gpc_index), bit value 1 indicates
* For s/w value nvgpu_gr_config_get_gpc_tpc_mask(gr->config, gpc_index), bit value 1 indicates
* corresponding TPC is enabled. But for h/w fuse register, bit value 1
* indicates corresponding TPC is disabled.
* So we need to flip the bits and ensure we don't write to bits greater
* than TPC count
*/
fuse_val = nvgpu_gr_config_get_gpc_tpc_mask(g->gr->config, gpc_index);
fuse_val = nvgpu_gr_config_get_gpc_tpc_mask(gr->config, gpc_index);
fuse_val = ~fuse_val;
fuse_val = fuse_val & 0xfU; /* tpc0_disable fuse is only 4-bit wide */
@@ -754,7 +757,7 @@ static void gv11b_gr_sm_stop_trigger_enable(struct gk20a *g)
{
u32 dbgr_control0;
u32 gpc, tpc, sm, gpc_offset, tpc_offset, offset;
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
/*
@@ -793,7 +796,7 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state)
/* Check if we have at least one valid warp
* get paused state on maxwell
*/
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc, tpc, sm, sm_id;
u32 offset;
u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0;
@@ -868,6 +871,7 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
int err;
struct nvgpu_tsg *tsg = nvgpu_tsg_from_ch(ch);
u32 flags = NVGPU_REG_OP_FLAG_MODE_ALL_OR_NONE;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
if (tsg == NULL) {
nvgpu_err(g, "gv11b_gr_set_sm_debug_mode failed=>tsg NULL");
@@ -892,21 +896,21 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g,
NVGPU_DEFAULT_SM_DIVERSITY_CONFIG) {
sm_info =
nvgpu_gr_config_get_sm_info(
g->gr->config, sm_id);
gr->config, sm_id);
} else {
sm_info =
nvgpu_gr_config_get_redex_sm_info(
g->gr->config, sm_id);
gr->config, sm_id);
}
#else
sm_info = nvgpu_gr_config_get_sm_info(g->gr->config, sm_id);
sm_info = nvgpu_gr_config_get_sm_info(gr->config, sm_id);
#endif
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
if (g->ops.gr.init.get_nonpes_aware_tpc != NULL) {
tpc = g->ops.gr.init.get_nonpes_aware_tpc(g,
nvgpu_gr_config_get_sm_info_gpc_index(sm_info),
nvgpu_gr_config_get_sm_info_tpc_index(sm_info),
g->gr->config);
gr->config);
} else {
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
}
@@ -980,7 +984,7 @@ static bool gv11b_gr_single_sm_debugger_attached(struct gk20a *g, u32 gpc,
bool gv11b_gr_sm_debugger_attached(struct gk20a *g)
{
u32 gpc, tpc, sm;
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
/* return true only if all SMs are in debug mode */
@@ -1045,7 +1049,7 @@ void gv11b_gr_suspend_single_sm(struct gk20a *g,
void gv11b_gr_suspend_all_sms(struct gk20a *g,
u32 global_esr_mask, bool check_errors)
{
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
u32 gpc, tpc, sm;
int err;
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
@@ -1178,7 +1182,7 @@ void gv11b_gr_resume_all_sms(struct gk20a *g)
{
u32 gpc, tpc, sm;
u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
struct nvgpu_gr *gr = g->gr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
if (!g->ops.gr.sm_debugger_attached(g)) {
nvgpu_err(g,
@@ -1638,6 +1642,7 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
u32 *priv_addr_table, u32 *t)
{
u32 priv_addr, gpc_addr;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
nvgpu_log_info(g, "addr=0x%x", addr);
@@ -1648,13 +1653,13 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
if ((broadcast_flags & PRI_BROADCAST_FLAGS_EGPC) != 0U) {
nvgpu_log_info(g, "broadcast flags egpc");
for (gpc_num = 0;
gpc_num < nvgpu_gr_config_get_gpc_count(g->gr->config);
gpc_num < nvgpu_gr_config_get_gpc_count(gr->config);
gpc_num++) {
if ((broadcast_flags & PRI_BROADCAST_FLAGS_ETPC) != 0U) {
nvgpu_log_info(g, "broadcast flags etpc");
for (tpc_num = 0;
tpc_num < nvgpu_gr_config_get_gpc_tpc_count(g->gr->config, gpc_num);
tpc_num < nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc_num);
tpc_num++) {
if ((broadcast_flags &
PRI_BROADCAST_FLAGS_SMPC) != 0U) {
@@ -1684,7 +1689,7 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
gpc_addr = pri_gpccs_addr_mask(g, priv_addr);
tpc_num = nvgpu_gr_get_tpc_num(g, gpc_addr);
if (tpc_num >= nvgpu_gr_config_get_gpc_tpc_count(g->gr->config, gpc_num)) {
if (tpc_num >= nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc_num)) {
continue;
}
@@ -1698,7 +1703,7 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
if ((broadcast_flags & PRI_BROADCAST_FLAGS_ETPC) != 0U) {
nvgpu_log_info(g, "broadcast flags etpc but not egpc");
for (tpc_num = 0;
tpc_num < nvgpu_gr_config_get_gpc_tpc_count(g->gr->config, gpc_num);
tpc_num < nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc_num);
tpc_num++) {
if ((broadcast_flags &
PRI_BROADCAST_FLAGS_SMPC) != 0U) {
@@ -1895,6 +1900,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
u32 broadcast_flags;
u32 t;
int err;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
t = 0;
*num_registers = 0;
@@ -1934,17 +1940,17 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
*/
if ((broadcast_flags & PRI_BROADCAST_FLAGS_GPC) != 0U) {
for (gpc_num = 0;
gpc_num < nvgpu_gr_config_get_gpc_count(g->gr->config);
gpc_num < nvgpu_gr_config_get_gpc_count(gr->config);
gpc_num++) {
if ((broadcast_flags & PRI_BROADCAST_FLAGS_TPC) != 0U) {
for (tpc_num = 0;
tpc_num < nvgpu_gr_config_get_gpc_tpc_count(g->gr->config, gpc_num);
tpc_num < nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc_num);
tpc_num++) {
if ((broadcast_flags &
PRI_BROADCAST_FLAGS_SM) != 0U) {
for (sm_num = 0;
sm_num < nvgpu_gr_config_get_sm_count_per_tpc(g->gr->config);
sm_num < nvgpu_gr_config_get_sm_count_per_tpc(gr->config);
sm_num++) {
priv_addr_table[t++] =
pri_sm_addr(g,
@@ -1971,7 +1977,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
gpc_addr = pri_gpccs_addr_mask(g, priv_addr);
tpc_num = nvgpu_gr_get_tpc_num(g, gpc_addr);
if (tpc_num >= nvgpu_gr_config_get_gpc_tpc_count(g->gr->config, gpc_num)) {
if (tpc_num >= nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc_num)) {
continue;
}
@@ -2010,7 +2016,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
}
for (gpc_num = 0;
gpc_num < nvgpu_gr_config_get_gpc_count(g->gr->config);
gpc_num < nvgpu_gr_config_get_gpc_count(gr->config);
gpc_num++) {
for (domain_idx = pmm_domain_start;
domain_idx < (pmm_domain_start + num_domains);
@@ -2064,7 +2070,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
} else if ((broadcast_flags & PRI_BROADCAST_FLAGS_GPC) == 0U) {
if ((broadcast_flags & PRI_BROADCAST_FLAGS_TPC) != 0U) {
for (tpc_num = 0;
tpc_num < nvgpu_gr_config_get_gpc_tpc_count(g->gr->config, gpc_num);
tpc_num < nvgpu_gr_config_get_gpc_tpc_count(gr->config, gpc_num);
tpc_num++) {
priv_addr_table[t++] =
pri_tpc_addr(g,
@@ -2089,6 +2095,7 @@ int gv11b_gr_clear_sm_error_state(struct gk20a *g,
u32 gpc, tpc, sm, offset;
u32 val;
struct nvgpu_tsg *tsg;
struct nvgpu_gr *gr = nvgpu_gr_get_cur_instance_ptr(g);
int err = 0;
@@ -2114,14 +2121,14 @@ int gv11b_gr_clear_sm_error_state(struct gk20a *g,
NVGPU_DEFAULT_SM_DIVERSITY_CONFIG) {
sm_info =
nvgpu_gr_config_get_sm_info(
g->gr->config, sm_id);
gr->config, sm_id);
} else {
sm_info =
nvgpu_gr_config_get_redex_sm_info(
g->gr->config, sm_id);
gr->config, sm_id);
}
#else
sm_info = nvgpu_gr_config_get_sm_info(g->gr->config, sm_id);
sm_info = nvgpu_gr_config_get_sm_info(gr->config, sm_id);
#endif
gpc = nvgpu_gr_config_get_sm_info_gpc_index(sm_info);
@@ -2129,7 +2136,7 @@ int gv11b_gr_clear_sm_error_state(struct gk20a *g,
tpc = g->ops.gr.init.get_nonpes_aware_tpc(g,
nvgpu_gr_config_get_sm_info_gpc_index(sm_info),
nvgpu_gr_config_get_sm_info_tpc_index(sm_info),
g->gr->config);
gr->config);
} else {
tpc = nvgpu_gr_config_get_sm_info_tpc_index(sm_info);
}