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git://nv-tegra.nvidia.com/linux-nvgpu.git
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gpu: nvgpu: add NVGPU_SUPPORT_COMPRESSION flag
Add NVGPU_SUPPORT_COMPRESSION to indicate if compression feature is supported in nvgpu. If not, set cbc.init, cbc.ctrl and cbc.alloc_comptags hals to NULL. Add corresponding GPU characteristics flag and IOCTL mapping to sync compression support status with nvrm_gpu. JIRA NVGPU-4666 Change-Id: I2e685688ddac592b3bb918ee70c82ea5524d695a Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2338926 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
committed by
Alex Waterman
parent
cfc5bac059
commit
ee216bc941
@@ -1241,6 +1241,16 @@ int gm20b_init_hal(struct gk20a *g)
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#endif
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#endif
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}
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}
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#ifdef CONFIG_NVGPU_COMPRESSION
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nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPRESSION, true);
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_COMPRESSION)) {
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gops->cbc.init = NULL;
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gops->cbc.ctrl = NULL;
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gops->cbc.alloc_comptags = NULL;
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}
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#endif
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#ifdef CONFIG_NVGPU_GRAPHICS
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#ifdef CONFIG_NVGPU_GRAPHICS
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nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, false);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, false);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, false);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, false);
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@@ -1342,6 +1342,16 @@ int gp10b_init_hal(struct gk20a *g)
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#endif
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#endif
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}
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}
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#ifdef CONFIG_NVGPU_COMPRESSION
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nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPRESSION, true);
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_COMPRESSION)) {
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gops->cbc.init = NULL;
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gops->cbc.ctrl = NULL;
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gops->cbc.alloc_comptags = NULL;
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}
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#endif
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#ifdef CONFIG_NVGPU_GRAPHICS
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#ifdef CONFIG_NVGPU_GRAPHICS
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nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, false);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_ZBC_STENCIL, false);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true);
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nvgpu_set_enabled(g, NVGPU_SUPPORT_PREEMPTION_GFXP, true);
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@@ -1587,6 +1587,16 @@ int gv11b_init_hal(struct gk20a *g)
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#endif
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#endif
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}
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}
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#ifdef CONFIG_NVGPU_COMPRESSION
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nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPRESSION, true);
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_COMPRESSION)) {
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gops->cbc.init = NULL;
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gops->cbc.ctrl = NULL;
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gops->cbc.alloc_comptags = NULL;
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}
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#endif
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nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
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nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
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#ifdef CONFIG_NVGPU_FECS_TRACE
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#ifdef CONFIG_NVGPU_FECS_TRACE
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
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nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true);
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@@ -1780,16 +1780,22 @@ int tu104_init_hal(struct gk20a *g)
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#ifdef CONFIG_NVGPU_DGPU
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#ifdef CONFIG_NVGPU_DGPU
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nvgpu_pramin_ops_init(g);
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nvgpu_pramin_ops_init(g);
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#endif
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#endif
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/* dGpu VDK support */
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#ifdef CONFIG_NVGPU_SIM
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)){
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/* Disable compression */
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#ifdef CONFIG_NVGPU_COMPRESSION
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#ifdef CONFIG_NVGPU_COMPRESSION
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if (!nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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nvgpu_set_enabled(g, NVGPU_SUPPORT_COMPRESSION, true);
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}
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if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_COMPRESSION)) {
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gops->cbc.init = NULL;
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gops->cbc.init = NULL;
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gops->cbc.ctrl = NULL;
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gops->cbc.ctrl = NULL;
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gops->cbc.alloc_comptags = NULL;
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gops->cbc.alloc_comptags = NULL;
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}
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#endif
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#endif
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/* dGpu VDK support */
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#ifdef CONFIG_NVGPU_SIM
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if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
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#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
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#ifdef CONFIG_NVGPU_GR_FALCON_NON_SECURE_BOOT
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gops->gr.falcon.load_ctxsw_ucode =
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gops->gr.falcon.load_ctxsw_ucode =
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nvgpu_gr_falcon_load_ctxsw_ucode;
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nvgpu_gr_falcon_load_ctxsw_ucode;
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@@ -252,10 +252,13 @@ struct gk20a;
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/** SM RAMS ECC is enabled */
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/** SM RAMS ECC is enabled */
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#define NVGPU_ECC_ENABLED_SM_RAMS 86U
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#define NVGPU_ECC_ENABLED_SM_RAMS 86U
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/** Enable compression */
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#define NVGPU_SUPPORT_COMPRESSION 87U
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/*
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/*
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* Must be greater than the largest bit offset in the above list.
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* Must be greater than the largest bit offset in the above list.
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*/
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*/
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#define NVGPU_MAX_ENABLED_BITS 87U
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#define NVGPU_MAX_ENABLED_BITS 88U
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/**
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/**
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* @brief Check if the passed flag is enabled.
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* @brief Check if the passed flag is enabled.
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@@ -250,7 +250,9 @@ static struct nvgpu_flags_mapping flags_mapping[] = {
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{NVGPU_GPU_FLAGS_SUPPORT_SET_CTX_MMU_DEBUG_MODE,
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{NVGPU_GPU_FLAGS_SUPPORT_SET_CTX_MMU_DEBUG_MODE,
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NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE},
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NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE},
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{NVGPU_GPU_FLAGS_SUPPORT_FAULT_RECOVERY,
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{NVGPU_GPU_FLAGS_SUPPORT_FAULT_RECOVERY,
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NVGPU_SUPPORT_FAULT_RECOVERY}
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NVGPU_SUPPORT_FAULT_RECOVERY},
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{NVGPU_GPU_FLAGS_SUPPORT_COMPRESSION,
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NVGPU_SUPPORT_COMPRESSION}
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};
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};
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static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)
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static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g)
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@@ -173,6 +173,8 @@ struct nvgpu_gpu_zbc_query_table_args {
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#define NVGPU_GPU_FLAGS_SUPPORT_SET_CTX_MMU_DEBUG_MODE (1ULL << 32)
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#define NVGPU_GPU_FLAGS_SUPPORT_SET_CTX_MMU_DEBUG_MODE (1ULL << 32)
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/* Fault recovery is enabled */
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/* Fault recovery is enabled */
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#define NVGPU_GPU_FLAGS_SUPPORT_FAULT_RECOVERY (1ULL << 33)
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#define NVGPU_GPU_FLAGS_SUPPORT_FAULT_RECOVERY (1ULL << 33)
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/* Compression is enabled */
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#define NVGPU_GPU_FLAGS_SUPPORT_COMPRESSION (1ULL << 34)
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/* SM LRF ECC is enabled */
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/* SM LRF ECC is enabled */
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#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
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#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
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/* SM SHM ECC is enabled */
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/* SM SHM ECC is enabled */
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