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gpu: nvgpu: add pmu hals to resolve mismatch

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Add the following HALs to avoid the duplication
of code for future chips:
- set_mailbox1
- get_ecc_address
- get_ecc_status
- set_ecc_status

JIRA NVGPU-9758

Change-Id: I54ce3dfaae2873dbcd88edabbd877eca9f3d1fdb
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2898016
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya
2023-05-03 15:36:08 +00:00
committed by mobile promotions
parent 24a533c9dc
commit ef1fb41e54
12 changed files with 54 additions and 15 deletions
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4
drivers/gpu/nvgpu/hal/init/hal_tu104.c
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@@ -1236,6 +1236,10 @@ static const struct gops_pmu tu104_ops_pmu = {
.pmu_mutex_release = gk20a_pmu_mutex_release,
.pmu_is_interrupted = gk20a_pmu_is_interrupted,
.get_irqmask = gk20a_pmu_get_irqmask,
.set_mailbox1 = gk20a_pmu_set_mailbox1,
.get_ecc_address = gv11b_pmu_get_ecc_address,
.get_ecc_status = gv11b_pmu_get_ecc_status,
.set_ecc_status = gv11b_pmu_set_ecc_status,
.get_irqstat = gk20a_pmu_get_irqstat,
.set_irqsclr = gk20a_pmu_set_irqsclr,
.set_irqsset = gk20a_pmu_set_irqsset,