nv-tegra-mirror/linux-nvgpu
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/linux-nvgpu.git synced 2025-12-24 10:34:43 +03:00
Code Issues Packages Projects Releases Wiki Activity

gpu: nvgpu: add pmu hals to resolve mismatch

Browse Source 
Add the following HALs to avoid the duplication
of code for future chips:
- set_mailbox1
- get_ecc_address
- get_ecc_status
- set_ecc_status

JIRA NVGPU-9758

Change-Id: I54ce3dfaae2873dbcd88edabbd877eca9f3d1fdb
Signed-off-by: Divya <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2898016
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya
2023-05-03 15:36:08 +00:00
committed by mobile promotions
parent 24a533c9dc
commit ef1fb41e54
12 changed files with 54 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/hal/pmu/pmu_ga10b.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -437,7 +437,7 @@ static int ga10b_pmu_handle_ecc(struct gk20a *g)
int ret = 0;
u32 ecc_status = 0;
ecc_status = nvgpu_readl(g, pwr_pmu_falcon_ecc_status_r());
ecc_status = g->ops.pmu.get_ecc_status(g);
if ((ecc_status &
pwr_pmu_falcon_ecc_status_uncorrected_err_imem_m()) != 0U) {
@@ -481,7 +481,7 @@ static int ga10b_pmu_handle_ecc(struct gk20a *g)
if (ret != 0) {
nvgpu_err(g, "ecc_addr(0x%x)",
nvgpu_readl(g, pwr_pmu_falcon_ecc_address_r()));
g->ops.pmu.get_ecc_address(g));
}
return ret;