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gpu: nvgpu: Add falcon gops

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Add falcon gops for accessing below constants. This is
required for nvgpu-next.

falcon_falcon_dmemc_blk_m
falcon_falcon_imemc_blk_f

JIRA NVGPU-4834

Change-Id: I1a60f473470a7a03fb31dceecfccd91fcc690de9
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2322736
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Divya Singhatwaria
2020-04-21 10:26:29 +05:30
committed by Alex Waterman
parent c060e754fc
commit f0896f94e1
8 changed files with 31 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -64,7 +64,7 @@ int gk20a_falcon_copy_from_dmem(struct nvgpu_falcon *flcn,
bytes = size & 0x3U; bytes = size & 0x3U;
addr_mask = falcon_falcon_dmemc_offs_m() | addr_mask = falcon_falcon_dmemc_offs_m() |
falcon_falcon_dmemc_blk_m(); g->ops.falcon.dmemc_blk_mask();
src &= addr_mask; src &= addr_mask;
@@ -107,7 +107,7 @@ int gk20a_falcon_copy_from_imem(struct nvgpu_falcon *flcn, u32 src,
nvgpu_writel(g, base_addr + falcon_falcon_imemc_r(port), nvgpu_writel(g, base_addr + falcon_falcon_imemc_r(port),
falcon_falcon_imemc_offs_f(src >> 2) | falcon_falcon_imemc_offs_f(src >> 2) |
falcon_falcon_imemc_blk_f(blk) | g->ops.falcon.imemc_blk_field(blk) |
falcon_falcon_dmemc_aincr_f(1)); falcon_falcon_dmemc_aincr_f(1));
for (i = 0; i < words; i++) { for (i = 0; i < words; i++) {

4
drivers/gpu/nvgpu/hal/falcon/falcon_gk20a.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -61,6 +61,8 @@
#define FALCON_DMEM_BLKSIZE2 8U #define FALCON_DMEM_BLKSIZE2 8U
u32 gk20a_falcon_dmemc_blk_mask(void);
u32 gk20a_falcon_imemc_blk_field(u32 blk);
void gk20a_falcon_reset(struct nvgpu_falcon *flcn); void gk20a_falcon_reset(struct nvgpu_falcon *flcn);
bool gk20a_is_falcon_cpu_halted(struct nvgpu_falcon *flcn); bool gk20a_is_falcon_cpu_halted(struct nvgpu_falcon *flcn);
bool gk20a_is_falcon_idle(struct nvgpu_falcon *flcn); bool gk20a_is_falcon_idle(struct nvgpu_falcon *flcn);

16
drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c
View File

@@ -29,6 +29,16 @@
#include <nvgpu/hw/gm20b/hw_falcon_gm20b.h> #include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
u32 gk20a_falcon_dmemc_blk_mask(void)
{
return falcon_falcon_dmemc_blk_m();
}
u32 gk20a_falcon_imemc_blk_field(u32 blk)
{
return falcon_falcon_imemc_blk_f(blk);
}
static inline u32 gk20a_falcon_readl(struct nvgpu_falcon *flcn, u32 offset) static inline u32 gk20a_falcon_readl(struct nvgpu_falcon *flcn, u32 offset)
{ {
return nvgpu_readl(flcn->g, return nvgpu_readl(flcn->g,
@@ -170,6 +180,7 @@ static void falcon_copy_to_dmem_unaligned_src(struct nvgpu_falcon *flcn,
int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn, int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
u32 dst, u8 *src, u32 size, u8 port) u32 dst, u8 *src, u32 size, u8 port)
{ {
struct gk20a *g = flcn->g;
u32 i = 0U, words = 0U, bytes = 0U; u32 i = 0U, words = 0U, bytes = 0U;
u32 data = 0U, addr_mask = 0U; u32 data = 0U, addr_mask = 0U;
u32 *src_u32 = NULL; u32 *src_u32 = NULL;
@@ -180,7 +191,7 @@ int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
bytes = size & 0x3U; bytes = size & 0x3U;
addr_mask = falcon_falcon_dmemc_offs_m() | addr_mask = falcon_falcon_dmemc_offs_m() |
falcon_falcon_dmemc_blk_m(); g->ops.falcon.dmemc_blk_mask();
dst &= addr_mask; dst &= addr_mask;
@@ -280,6 +291,7 @@ static void falcon_copy_to_imem_unaligned_src(struct nvgpu_falcon *flcn,
int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst,
u8 *src, u32 size, u8 port, bool sec, u32 tag) u8 *src, u32 size, u8 port, bool sec, u32 tag)
{ {
struct gk20a *g = flcn->g;
u32 *src_u32 = NULL; u32 *src_u32 = NULL;
u32 words = 0U; u32 words = 0U;
u32 blk = 0U; u32 blk = 0U;
@@ -295,7 +307,7 @@ int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst,
gk20a_falcon_writel(flcn, falcon_falcon_imemc_r(port), gk20a_falcon_writel(flcn, falcon_falcon_imemc_r(port),
falcon_falcon_imemc_offs_f(dst >> 2) | falcon_falcon_imemc_offs_f(dst >> 2) |
falcon_falcon_imemc_blk_f(blk) | g->ops.falcon.imemc_blk_field(blk) |
/* Set Auto-Increment on write */ /* Set Auto-Increment on write */
falcon_falcon_imemc_aincw_f(1) | falcon_falcon_imemc_aincw_f(1) |
falcon_falcon_imemc_secure_f(sec ? 1U : 0U)); falcon_falcon_imemc_secure_f(sec ? 1U : 0U));

2
drivers/gpu/nvgpu/hal/init/hal_gm20b.c
View File

@@ -1062,6 +1062,8 @@ static const struct gpu_ops gm20b_ops = {
.get_ports_count = gk20a_falcon_get_ports_count, .get_ports_count = gk20a_falcon_get_ports_count,
.copy_to_dmem = gk20a_falcon_copy_to_dmem, .copy_to_dmem = gk20a_falcon_copy_to_dmem,
.copy_to_imem = gk20a_falcon_copy_to_imem, .copy_to_imem = gk20a_falcon_copy_to_imem,
.dmemc_blk_mask = gk20a_falcon_dmemc_blk_mask,
.imemc_blk_field = gk20a_falcon_imemc_blk_field,
.bootstrap = gk20a_falcon_bootstrap, .bootstrap = gk20a_falcon_bootstrap,
.mailbox_read = gk20a_falcon_mailbox_read, .mailbox_read = gk20a_falcon_mailbox_read,
.mailbox_write = gk20a_falcon_mailbox_write, .mailbox_write = gk20a_falcon_mailbox_write,

2
drivers/gpu/nvgpu/hal/init/hal_gp10b.c
View File

@@ -1168,6 +1168,8 @@ static const struct gpu_ops gp10b_ops = {
.get_ports_count = gk20a_falcon_get_ports_count, .get_ports_count = gk20a_falcon_get_ports_count,
.copy_to_dmem = gk20a_falcon_copy_to_dmem, .copy_to_dmem = gk20a_falcon_copy_to_dmem,
.copy_to_imem = gk20a_falcon_copy_to_imem, .copy_to_imem = gk20a_falcon_copy_to_imem,
.dmemc_blk_mask = gk20a_falcon_dmemc_blk_mask,
.imemc_blk_field = gk20a_falcon_imemc_blk_field,
.bootstrap = gk20a_falcon_bootstrap, .bootstrap = gk20a_falcon_bootstrap,
.mailbox_read = gk20a_falcon_mailbox_read, .mailbox_read = gk20a_falcon_mailbox_read,
.mailbox_write = gk20a_falcon_mailbox_write, .mailbox_write = gk20a_falcon_mailbox_write,

2
drivers/gpu/nvgpu/hal/init/hal_gv11b.c
View File

@@ -1423,6 +1423,8 @@ NVGPU_COV_WHITELIST_BLOCK_END(NVGPU_MISRA(Rule, 8_7))
.get_ports_count = gk20a_falcon_get_ports_count, .get_ports_count = gk20a_falcon_get_ports_count,
.copy_to_dmem = gk20a_falcon_copy_to_dmem, .copy_to_dmem = gk20a_falcon_copy_to_dmem,
.copy_to_imem = gk20a_falcon_copy_to_imem, .copy_to_imem = gk20a_falcon_copy_to_imem,
.dmemc_blk_mask = gk20a_falcon_dmemc_blk_mask,
.imemc_blk_field = gk20a_falcon_imemc_blk_field,
.bootstrap = gk20a_falcon_bootstrap, .bootstrap = gk20a_falcon_bootstrap,
.mailbox_read = gk20a_falcon_mailbox_read, .mailbox_read = gk20a_falcon_mailbox_read,
.mailbox_write = gk20a_falcon_mailbox_write, .mailbox_write = gk20a_falcon_mailbox_write,

2
drivers/gpu/nvgpu/hal/init/hal_tu104.c
View File

@@ -1468,6 +1468,8 @@ static const struct gpu_ops tu104_ops = {
.get_ports_count = gk20a_falcon_get_ports_count, .get_ports_count = gk20a_falcon_get_ports_count,
.copy_to_dmem = gk20a_falcon_copy_to_dmem, .copy_to_dmem = gk20a_falcon_copy_to_dmem,
.copy_to_imem = gk20a_falcon_copy_to_imem, .copy_to_imem = gk20a_falcon_copy_to_imem,
.dmemc_blk_mask = gk20a_falcon_dmemc_blk_mask,
.imemc_blk_field = gk20a_falcon_imemc_blk_field,
.bootstrap = gk20a_falcon_bootstrap, .bootstrap = gk20a_falcon_bootstrap,
.mailbox_read = gk20a_falcon_mailbox_read, .mailbox_read = gk20a_falcon_mailbox_read,
.mailbox_write = gk20a_falcon_mailbox_write, .mailbox_write = gk20a_falcon_mailbox_write,

4
drivers/gpu/nvgpu/include/nvgpu/gops_falcon.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -50,6 +50,8 @@ struct gops_falcon {
int (*copy_to_imem)(struct nvgpu_falcon *flcn, int (*copy_to_imem)(struct nvgpu_falcon *flcn,
u32 dst, u8 *src, u32 size, u8 port, u32 dst, u8 *src, u32 size, u8 port,
bool sec, u32 tag); bool sec, u32 tag);
u32 (*dmemc_blk_mask)(void);
u32 (*imemc_blk_field)(u32 blk);
void (*bootstrap)(struct nvgpu_falcon *flcn, void (*bootstrap)(struct nvgpu_falcon *flcn,
u32 boot_vector); u32 boot_vector);
u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 (*mailbox_read)(struct nvgpu_falcon *flcn,