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gpu: nvgpu: Support change_seq structure as per latest ucode

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Some of the perameters in change seq script is modified
in latest r435 saftey ucode. Done changes on NVGPU to
support the same.

NVGPU-3777

Change-Id: I625b41686ed97d9c41c5955b226e0c20a6271db8
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2153118
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
rmylavarapu
2019-07-15 10:07:25 +05:30
committed by mobile promotions
parent 322d0a0cd8
commit f0a8daee02
6 changed files with 40 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlclk.h
View File

@@ -265,6 +265,19 @@ struct ctrl_clk_clk_domain_list {
clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
};
struct ctrl_clk_domain_clk_mon_item {
u32 clk_api_domain;
u32 clk_freq_Mhz;
u32 low_threshold_percentage;
u32 high_threshold_percentage;
};
struct ctrl_clk_domain_clk_mon_list {
u8 num_domain;
struct ctrl_clk_domain_clk_mon_item
clk_domain[CTRL_CLK_CLK_DOMAIN_CLIENT_MAX_DOMAINS];
};
#define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \
((pvfpair)->freq_mhz)

11
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlclkavfs.h
View File

@@ -78,4 +78,15 @@
#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_MIN (0x00000001U)
#define CTRL_CLK_VIN_SW_OVERRIDE_VIN_USE_SW_REQ (0x00000003U)
struct ctrl_clk_vin_sw_override_list_item {
u8 override_mode;
u32 voltage_uV;
};
struct ctrl_clk_vin_sw_override_list {
struct ctrl_boardobjgrp_mask_e32 volt_rails_mask;
struct ctrl_clk_vin_sw_override_list_item
volt[4];
};
#endif /* NVGPU_PMUIF_CTRLCLKAVFS_H */

13
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlperf.h
View File

@@ -218,9 +218,11 @@ enum ctrl_perf_change_seq_pmu_step_id {
CTRL_PERF_CHANGE_SEQ_31_STEP_ID_NOISE_AWARE_CLKS,
CTRL_PERF_CHANGE_SEQ_35_STEP_ID_PRE_VOLT_CLKS,
CTRL_PERF_CHANGE_SEQ_35_STEP_ID_POST_VOLT_CLKS,
CTRL_PERF_CHANGE_SEQ_PMU_STEP_ID_MAX_STEPS,
CTRL_PERF_CHANGE_SEQ_PMU_STEP_ID_MAX_STEPS = 26,
};
#define CTRL_PERF_CHANGE_SEQ_SCRIPT_VF_SWITCH_MAX_STEPS 13U
struct ctrl_perf_change_seq_step_profiling {
/*all aligned to 32 */
u64 total_timens;
@@ -257,13 +259,19 @@ struct ctrl_perf_change_seq_pmu_script_step_bif {
struct ctrl_perf_change_seq_pmu_script_step_clks {
struct ctrl_perf_change_seq_pmu_script_step_super super;
struct ctrl_volt_volt_rail_list_v1 volt_list;
struct ctrl_clk_clk_domain_list clk_list;
struct ctrl_clk_vin_sw_override_list vin_sw_override_list;
};
struct ctrl_perf_change_seq_pmu_script_step_volt {
struct ctrl_perf_change_seq_pmu_script_step_super super;
struct ctrl_volt_volt_rail_list_v1 volt_list;
struct ctrl_clk_vin_sw_override_list vin_sw_override_list;
};
struct ctrl_perf_change_seq_pmu_script_step_clk_mon {
struct ctrl_perf_change_seq_pmu_script_step_super super;
struct ctrl_clk_domain_clk_mon_list clk_mon_list;
};
union ctrl_perf_change_seq_pmu_script_step_data {
@@ -274,6 +282,7 @@ union ctrl_perf_change_seq_pmu_script_step_data {
struct ctrl_perf_change_seq_pmu_script_step_bif bif;
struct ctrl_perf_change_seq_pmu_script_step_clks clk;
struct ctrl_perf_change_seq_pmu_script_step_volt volt;
struct ctrl_perf_change_seq_pmu_script_step_clk_mon clk_mon;
};
#endif /* NVGPU_PMUIF_CTRLPERF_H */

3
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/ctrlvolt.h
View File

@@ -134,12 +134,13 @@ struct ctrl_volt_volt_rail_list_item_v1 {
u8 rail_idx;
u32 voltage_uv;
u32 voltage_min_noise_unaware_uv;
u32 voltage_offset_uV[2];
};
struct ctrl_volt_volt_rail_list_v1 {
u8 num_rails;
struct ctrl_volt_volt_rail_list_item_v1
rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS];
rails[CTRL_VOLT_VOLT_RAIL_CLIENT_MAX_RAILS];
};
#endif /* NVGPU_PMUIF_CTRLVOLT_H */

3
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/perf.h
View File

@@ -176,6 +176,7 @@ struct nv_pmu_perf_change_seq_super_info_set {
u8 version;
struct ctrl_boardobjgrp_mask_e32 clk_domains_exclusion_mask;
struct ctrl_boardobjgrp_mask_e32 clk_domains_inclusion_mask;
u32 strp_id_exclusive_mask;
};
struct nv_pmu_perf_change_seq_pmu_info_set {
@@ -213,7 +214,7 @@ struct perf_change_seq_pmu_script {
union ctrl_perf_change_seq_change_aligned change;
/* below should be an aligned structure */
union ctrl_perf_change_seq_pmu_script_step_data_aligned
steps[CTRL_PERF_CHANGE_SEQ_PMU_STEP_ID_MAX_STEPS];
steps[CTRL_PERF_CHANGE_SEQ_SCRIPT_VF_SWITCH_MAX_STEPS];
};
struct nv_pmu_rpc_struct_perf_vfe_eval {

1
drivers/gpu/nvgpu/include/nvgpu/pmu/pmuif/volt.h
View File

@@ -53,6 +53,7 @@ struct nv_pmu_volt_volt_rail_boardobj_set {
u8 volt_dev_idx_default;
u8 volt_dev_idx_ipc_vmin;
u8 volt_scale_exp_pwr_equ_idx;
struct ctrl_boardobjgrp_mask_e32 vin_dev_mask;
struct ctrl_boardobjgrp_mask_e32 volt_dev_mask;
s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
};