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gpu: nvgpu: Add tests for code coverage in gr.falcon
Add more tests for branch and line coverages in gr.falcon common and hal code. Jira NVGPU-4453 Change-Id: Ie01bac73ad18773bba1c27bf4bcb2b2776970f29 Signed-off-by: vinodg <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2258557 Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
vinodg
@@ -70,6 +70,7 @@ gm20b_priv_set_timeout_settings
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gm20b_priv_ring_enum_ltc
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gm20b_priv_ring_get_gpc_count
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gm20b_priv_ring_get_fbp_count
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gm20b_gr_falcon_submit_fecs_method_op
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gp10b_ce_nonstall_isr
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gp10b_get_max_page_table_levels
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gp10b_mm_get_default_big_page_size
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@@ -396,6 +397,7 @@ nvgpu_init_enabled_flags
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nvgpu_init_hal
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nvgpu_init_mm_support
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nvgpu_inst_block_addr
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nvgpu_free_inst_block
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nvgpu_inst_block_ptr
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nvgpu_is_enabled
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nvgpu_big_alloc_impl
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@@ -1847,6 +1847,18 @@
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"unit": "nvgpu_gr_falcon",
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"test_level": 0
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},
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{
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"test": "test_gr_falcon_fail_ctxsw_ucode",
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"case": "gr_falcon_fail_ctxsw_ucode",
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"unit": "nvgpu_gr_falcon",
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"test_level": 0
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},
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{
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"test": "test_gr_falcon_gk20a_ctrl_ctxsw",
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"case": "gr_falcon_gk20a_ctrl_ctxsw",
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"unit": "nvgpu_gr_falcon",
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"test_level": 0
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},
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{
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"test": "test_gr_falcon_deinit",
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"case": "gr_falcon_deinit",
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@@ -20,7 +20,9 @@
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.SUFFIXES:
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OBJS = nvgpu-gr-falcon.o
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OBJS = nvgpu-gr-falcon.o \
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nvgpu-gr-falcon-gk20a.o
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MODULE = nvgpu-gr-falcon
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LIB_PATHS += -lnvgpu-gr
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@@ -25,7 +25,8 @@
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###############################################################################
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NVGPU_UNIT_NAME = nvgpu-gr-falcon
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NVGPU_UNIT_SRCS = nvgpu-gr-falcon.c
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NVGPU_UNIT_SRCS = nvgpu-gr-falcon.c \
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nvgpu-gr-falcon-gk20a.c
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NVGPU_UNIT_INTERFACE_DIRS := \
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$(NV_COMPONENT_DIR)/.. \
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268
userspace/units/gr/falcon/nvgpu-gr-falcon-gk20a.c
Normal file
268
userspace/units/gr/falcon/nvgpu-gr-falcon-gk20a.c
Normal file
@@ -0,0 +1,268 @@
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/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <stdlib.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include <unit/io.h>
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#include <unit/unit.h>
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#include <nvgpu/posix/io.h>
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#include <nvgpu/posix/timers.h>
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#include <nvgpu/posix/posix-fault-injection.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/gr/gr.h>
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#include <nvgpu/gr/gr_falcon.h>
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#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
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#include "common/gr/gr_priv.h"
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#include "common/gr/gr_falcon_priv.h"
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#include "hal/gr/falcon/gr_falcon_gm20b.h"
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#include "../nvgpu-gr.h"
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#include "nvgpu-gr-falcon-gk20a.h"
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struct gr_falcon_gk20a_fecs_op {
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u32 id;
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u32 data;
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u32 ok;
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u32 fail;
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u32 cond_ok;
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u32 cond_fail;
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u32 result;
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};
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static void gr_falcon_fecs_dump_stats(struct gk20a *g)
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{
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/* Do Nothing */
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}
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static int gr_falcon_gk20a_submit_fecs_mthd_op(struct unit_module *m,
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struct gk20a *g)
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{
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int err, i;
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struct nvgpu_fecs_method_op op = {
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.mailbox = { .id = 4U, .data = 0U, .ret = NULL,
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.clr = ~U32(0U), .ok = 0U, .fail = 0U},
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.method.data = 0U,
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.cond.ok = GR_IS_UCODE_OP_SKIP,
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.cond.fail = GR_IS_UCODE_OP_SKIP,
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};
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struct gr_falcon_gk20a_fecs_op fecs_op_stat[] = {
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[0] = {
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.id = 4U,
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.data = 0U,
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.ok = 0U,
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.fail = 0U,
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.cond_ok = GR_IS_UCODE_OP_SKIP,
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.cond_fail = GR_IS_UCODE_OP_SKIP,
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.result = 0U,
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},
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[1] = {
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.id = 2U,
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.data = 1U,
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.ok = 0U,
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.fail = 2U,
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.cond_ok = GR_IS_UCODE_OP_SKIP,
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.cond_fail = GR_IS_UCODE_OP_LESSER_EQUAL,
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.result = 1U,
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},
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[2] = {
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.id = 2U,
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.data = 1U,
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.ok = 2U,
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.fail = 0U,
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.cond_ok = GR_IS_UCODE_OP_LESSER_EQUAL,
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.cond_fail = 10,
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.result = 1U,
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},
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[3] = {
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.id = 2U,
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.data = 1U,
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.ok = 2U,
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.fail = 1U,
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.cond_ok = GR_IS_UCODE_OP_LESSER,
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.cond_fail = GR_IS_UCODE_OP_EQUAL,
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.result = 1U,
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},
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[4] = {
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.id = 2U,
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.data = 1U,
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.ok = 0U,
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.fail = 1U,
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.cond_ok = GR_IS_UCODE_OP_LESSER_EQUAL,
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.cond_fail = GR_IS_UCODE_OP_AND,
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.result = 1U,
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},
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[5] = {
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.id = 2U,
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.data = 1U,
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.ok = 0U,
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.fail = 2U,
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.cond_ok = GR_IS_UCODE_OP_LESSER,
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.cond_fail = GR_IS_UCODE_OP_LESSER,
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.result = 1U,
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},
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[6] = {
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.id = 2U,
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.data = 1U,
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.ok = 1U,
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.fail = 2U,
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.cond_ok = GR_IS_UCODE_OP_NOT_EQUAL,
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.cond_fail = GR_IS_UCODE_OP_NOT_EQUAL,
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.result = 1U,
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},
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[7] = {
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.id = 2U,
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.data = 1U,
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.ok = 1U,
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.fail = 2U,
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.cond_ok = GR_IS_UCODE_OP_EQUAL,
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.cond_fail = GR_IS_UCODE_OP_EQUAL,
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.result = 0U,
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},
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};
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int arry_cnt = sizeof(fecs_op_stat)/
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sizeof(struct gr_falcon_gk20a_fecs_op);
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g->ops.gr.falcon.dump_stats = gr_falcon_fecs_dump_stats;
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for (i = 0; i < arry_cnt; i++) {
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op.mailbox.ok = fecs_op_stat[i].ok;
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op.mailbox.fail = fecs_op_stat[i].fail;
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op.mailbox.id = fecs_op_stat[i].id;
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op.mailbox.data = fecs_op_stat[i].data;
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op.cond.ok = fecs_op_stat[i].cond_ok;
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op.cond.fail = fecs_op_stat[i].cond_fail;
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err = gm20b_gr_falcon_submit_fecs_method_op(g, op, false);
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if ((fecs_op_stat[i].result == 0) && err) {
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unit_return_fail(m, "submit_fecs_method_op failed\n");
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} else if (fecs_op_stat[i].result && (err == 0)){
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unit_return_fail(m, "submit_fecs_method_op failed\n");
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}
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}
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return UNIT_SUCCESS;
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}
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static int gr_falcon_timer_init_error(struct unit_module *m,
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struct gk20a *g)
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{
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int err, i;
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u32 fecs_imem = 0, gpccs_imem = 0;
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struct nvgpu_gr_falcon_query_sizes sizes;
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struct nvgpu_posix_fault_inj *timer_fi =
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nvgpu_timers_get_fault_injection();
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nvgpu_posix_enable_fault_injection(timer_fi, true, 0);
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err = g->ops.gr.falcon.wait_mem_scrubbing(g);
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nvgpu_posix_enable_fault_injection(timer_fi, false, 0);
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if (err == 0) {
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unit_return_fail(m,
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"gr_falcon_wait_mem_scrubbing timer failed\n");
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}
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for (i = 0; i < 2; i++) {
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switch (i) {
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case 0:
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fecs_imem = gr_fecs_dmactl_imem_scrubbing_m();
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break;
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case 1:
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fecs_imem = 0;
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gpccs_imem = gr_gpccs_dmactl_imem_scrubbing_m();
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break;
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}
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nvgpu_posix_io_writel_reg_space(g, gr_fecs_dmactl_r(),
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fecs_imem);
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nvgpu_posix_io_writel_reg_space(g, gr_gpccs_dmactl_r(),
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gpccs_imem);
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err = g->ops.gr.falcon.wait_mem_scrubbing(g);
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if (err == 0) {
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unit_return_fail(m,
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"gr_falcon_wait_mem_scrubbing case %d failed\n", i);
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}
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}
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nvgpu_posix_enable_fault_injection(timer_fi, true, 0);
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err = g->ops.gr.falcon.wait_ctxsw_ready(g);
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nvgpu_posix_enable_fault_injection(timer_fi, false, 0);
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if (err == 0) {
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unit_return_fail(m,
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"gr_falcon_wait_ctxsw_ready timer failed\n");
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}
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nvgpu_posix_enable_fault_injection(timer_fi, true, 0);
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err = g->ops.gr.falcon.init_ctx_state(g, &sizes);
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nvgpu_posix_enable_fault_injection(timer_fi, false, 0);
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if (err == 0) {
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unit_return_fail(m,
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"gr_falcon_init_ctx_state failed\n");
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}
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/* branch coverage check */
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nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false);
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nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
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err = g->ops.gr.falcon.wait_ctxsw_ready(g);
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if (err != 0) {
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unit_return_fail(m,
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"gr_falcon_wait_ctxsw_ready failed\n");
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}
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nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
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return UNIT_SUCCESS;
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}
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int test_gr_falcon_gk20a_ctrl_ctxsw(struct unit_module *m,
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struct gk20a *g, void *args)
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{
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int err = 0;
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u32 data = 0;
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err = g->ops.gr.falcon.ctrl_ctxsw(g,
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NVGPU_GR_FALCON_METHOD_GOLDEN_IMAGE_SAVE, data, NULL);
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if (err) {
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unit_return_fail(m, "falcon_gk20a_ctrl_ctxsw failed\n");
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}
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/* Invalid Method */
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err = g->ops.gr.falcon.ctrl_ctxsw(g, 0, data, NULL);
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if (err) {
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unit_return_fail(m, "falcon_gk20a_ctrl_ctxsw failed\n");
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}
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err = gr_falcon_timer_init_error(m, g);
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if (err) {
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unit_return_fail(m, "gr_falcon_timer_init_error failed\n");
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}
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err = gr_falcon_gk20a_submit_fecs_mthd_op(m, g);
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if (err) {
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unit_return_fail(m, "gr_falcon_gk20a_fecs_mthd_op failed\n");
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}
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return UNIT_SUCCESS;
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}
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70
userspace/units/gr/falcon/nvgpu-gr-falcon-gk20a.h
Normal file
70
userspace/units/gr/falcon/nvgpu-gr-falcon-gk20a.h
Normal file
@@ -0,0 +1,70 @@
|
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/*
|
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
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#ifndef UNIT_NVGPU_GR_FALCON_GK20A_H
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#define UNIT_NVGPU_GR_FALCON_GK20A_H
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#include <nvgpu/types.h>
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struct unit_module;
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struct gk20a;
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/** @addtogroup SWUTS-gr-falcon
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* @{
|
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*
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* Software Unit Test Specification for common.gr.falcon
|
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*/
|
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/**
|
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* Test specification for: test_gr_falcon_gk20a_ctrl_ctxsw
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*
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* Description: Helps to verify various failure and conditional checking
|
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* in falcon gm20b hal functions.
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*
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* Test Type: Error injection
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*
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* Input: #test_fifo_init_support() run for this GPU
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*
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* Targets: gm20b_gr_falcon_wait_mem_scrubbing,
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* gm20b_gr_falcon_wait_ctxsw_ready,
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* gm20b_gr_falcon_init_ctx_state,
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* gm20b_gr_falcon_submit_fecs_method_op,
|
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* gm20b_gr_falcon_ctrl_ctxsw.
|
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*
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* Steps:
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* - Call g->ops.gr.falcon.ctrl_ctxsw with Invalid Method.
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* - Enable timer init failure injection in various functions.
|
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* - g->ops.gr.falcon.wait_ctxsw_ready.
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* - g->ops.gr.falcon.init_ctx_state.
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* - g->ops.gr.falcon.wait_mem_scrubbing.
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* - Call gm20b_gr_falcon_submit_fecs_method_op with various
|
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* method op codes.
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* - Check that enable_set bit is set for ccsr_channel_r
|
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*
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* Output: Returns PASS if all branches gave expected results. FAIL otherwise.
|
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*/
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int test_gr_falcon_gk20a_ctrl_ctxsw(struct unit_module *m,
|
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struct gk20a *g, void *args);
|
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/**
|
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* @}
|
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*/
|
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#endif /* UNIT_NVGPU_GR_FALCON_GK20A_H */
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@@ -35,12 +35,16 @@
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#include <nvgpu/gr/gr.h>
|
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#include <nvgpu/gr/gr_falcon.h>
|
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|
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#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
|
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|
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#include "common/gr/gr_priv.h"
|
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#include "common/gr/gr_falcon_priv.h"
|
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#include "common/acr/acr_priv.h"
|
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#include "hal/gr/falcon/gr_falcon_gm20b.h"
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#include "../nvgpu-gr.h"
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#include "nvgpu-gr-falcon-gk20a.h"
|
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#include "nvgpu-gr-falcon.h"
|
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|
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struct gr_gops_falcon_orgs {
|
||||
@@ -92,6 +96,8 @@ int test_gr_falcon_init(struct unit_module *m,
|
||||
struct gk20a *g, void *args)
|
||||
{
|
||||
int err = 0;
|
||||
u32 fecs_base, ctx_state_rev_id;
|
||||
u32 gpccs_base, gpccs_start_offset;
|
||||
struct nvgpu_posix_fault_inj *kmem_fi =
|
||||
nvgpu_kmem_get_fault_injection();
|
||||
|
||||
@@ -118,17 +124,66 @@ int test_gr_falcon_init(struct unit_module *m,
|
||||
unit_return_fail(m, "nvgpu_gr_falcon_init_support failed\n");
|
||||
}
|
||||
|
||||
fecs_base = g->ops.gr.falcon.fecs_base_addr();
|
||||
if (fecs_base == 0) {
|
||||
unit_return_fail(m, "Get fecs_base failed\n");
|
||||
}
|
||||
|
||||
gpccs_base = g->ops.gr.falcon.gpccs_base_addr();
|
||||
if (gpccs_base == 0) {
|
||||
unit_return_fail(m, "Get gpccs_base failed\n");
|
||||
}
|
||||
|
||||
gpccs_start_offset = g->ops.gr.falcon.get_gpccs_start_reg_offset();
|
||||
if (gpccs_start_offset == 0) {
|
||||
unit_return_fail(m, "Get gpccs_base start failed\n");
|
||||
}
|
||||
|
||||
ctx_state_rev_id =
|
||||
g->ops.gr.falcon.get_fecs_ctx_state_store_major_rev_id(g);
|
||||
if (ctx_state_rev_id != 0) {
|
||||
unit_return_fail(m, "ctx_state rev_id failed\n");
|
||||
}
|
||||
|
||||
return UNIT_SUCCESS;
|
||||
}
|
||||
|
||||
static int gr_falcon_bind_instblk(struct unit_module *m, struct gk20a *g)
|
||||
{
|
||||
int err;
|
||||
struct nvgpu_ctxsw_ucode_info *ucode_info =
|
||||
&unit_gr_falcon->ctxsw_ucode_info;
|
||||
|
||||
err = nvgpu_alloc_inst_block(g, &ucode_info->inst_blk_desc);
|
||||
if (err != 0)
|
||||
return UNIT_FAIL;
|
||||
|
||||
g->ops.gr.falcon.bind_instblk = gr_falcon_gops.bind_instblk;
|
||||
err = nvgpu_gr_falcon_init_ctxsw(g, unit_gr_falcon);
|
||||
if (err != 0) {
|
||||
unit_return_fail(m,
|
||||
"falcon_init_ctxsw secure recovery failed\n");
|
||||
}
|
||||
|
||||
/* Set ctxsw_status_busy for branch coverage */
|
||||
nvgpu_posix_io_writel_reg_space(g, gr_fecs_ctxsw_status_1_r(),
|
||||
(0x1U << 12U));
|
||||
err = nvgpu_gr_falcon_init_ctxsw(g, unit_gr_falcon);
|
||||
if (err != 0) {
|
||||
unit_return_fail(m,
|
||||
"falcon_init_ctxsw secure recovery failed\n");
|
||||
}
|
||||
|
||||
nvgpu_free_inst_block(g, &ucode_info->inst_blk_desc);
|
||||
return err;
|
||||
}
|
||||
|
||||
int test_gr_falcon_init_ctxsw(struct unit_module *m,
|
||||
struct gk20a *g, void *args)
|
||||
{
|
||||
int err = 0;
|
||||
struct nvgpu_acr gr_falcon_acr_test;
|
||||
|
||||
unit_gr_falcon->ctxsw_ucode_info.gpccs.boot_signature =
|
||||
FALCON_UCODE_SIG_T18X_GPCCS_WITH_RESERVED;
|
||||
/* Test secure gpccs */
|
||||
err = nvgpu_gr_falcon_init_ctxsw(g, unit_gr_falcon);
|
||||
if (err) {
|
||||
@@ -153,6 +208,13 @@ int test_gr_falcon_init_ctxsw(struct unit_module *m,
|
||||
"falcon_init_ctxsw secure recovery failed\n");
|
||||
}
|
||||
|
||||
/* Test for falcon bind instblk */
|
||||
err = gr_falcon_bind_instblk(m, g);
|
||||
if (err != 0) {
|
||||
unit_return_fail(m,
|
||||
"falcon_bind_instblk failed\n");
|
||||
}
|
||||
|
||||
return UNIT_SUCCESS;
|
||||
}
|
||||
|
||||
@@ -276,6 +338,8 @@ struct unit_module_test nvgpu_gr_falcon_tests[] = {
|
||||
test_gr_falcon_init_ctx_state, NULL, 0),
|
||||
UNIT_TEST(gr_falcon_fail_ctxsw_ucode,
|
||||
test_gr_falcon_fail_ctxsw_ucode, NULL, 0),
|
||||
UNIT_TEST(gr_falcon_gk20a_ctrl_ctxsw,
|
||||
test_gr_falcon_gk20a_ctrl_ctxsw, NULL, 0),
|
||||
UNIT_TEST(gr_falcon_deinit, test_gr_falcon_deinit, NULL, 0),
|
||||
};
|
||||
|
||||
|
||||
@@ -652,11 +652,11 @@ int test_gr_intr_fecs_exceptions(struct unit_module *m,
|
||||
struct gk20a *g, void *args)
|
||||
{
|
||||
int err, i, j = 0;
|
||||
int arry_cnt = 10;
|
||||
int arry_cnt = 11;
|
||||
|
||||
u32 fecs_status[10] = {
|
||||
u32 fecs_status[11] = {
|
||||
0,
|
||||
gr_fecs_host_int_enable_ctxsw_intr0_enable_f() |
|
||||
gr_fecs_host_int_enable_ctxsw_intr0_enable_f(),
|
||||
gr_fecs_host_int_enable_ctxsw_intr1_enable_f(),
|
||||
gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(),
|
||||
gr_fecs_host_int_enable_umimp_firmware_method_enable_f(),
|
||||
|
||||
Reference in New Issue
Block a user