gpu: nvgpu: gr: use enum for global_ctx_buffer_index

Change the global_ctx_buffer_index member in the nvgpu_gr_ctx struct
to be an enum nvgpu_gr_global_ctx_index. global_ctx_buffer_index is
used as an array of these indicies, but had been declared as an int.
This change resolves a number of MISRA Rule 10.3 violations for implicit
assignment of objects of different essential or narrower type.

In order to use this enum, it is moved out of global_ctx.h into a new
header file ctx_common.h that can be used by both ctx.h and global_ctx.h.

JIRA NVGPU-2955

Change-Id: I5e399ba3b0821d696aa0b9909d3bc6bbe99d274c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075753
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Philip Elcan
2019-03-18 13:59:14 -04:00
committed by mobile promotions
parent c087e2c12e
commit f180ad0199
2 changed files with 5 additions and 3 deletions

View File

@@ -317,7 +317,8 @@ static void nvgpu_gr_ctx_unmap_global_ctx_buffers(struct gk20a *g,
struct vm_gk20a *vm)
{
u64 *g_bfr_va = gr_ctx->global_ctx_buffer_va;
int *g_bfr_index = gr_ctx->global_ctx_buffer_index;
enum nvgpu_gr_global_ctx_index *g_bfr_index =
gr_ctx->global_ctx_buffer_index;
u32 i;
nvgpu_log_fn(g, " ");
@@ -339,7 +340,7 @@ int nvgpu_gr_ctx_map_global_ctx_buffers(struct gk20a *g,
struct vm_gk20a *vm, bool vpr)
{
u64 *g_bfr_va;
int *g_bfr_index;
enum nvgpu_gr_global_ctx_index *g_bfr_index;
u64 gpu_va = 0ULL;
nvgpu_log_fn(g, " ");

View File

@@ -25,6 +25,7 @@
#include <nvgpu/types.h>
#include <nvgpu/nvgpu_mem.h>
#include <nvgpu/gr/global_ctx.h>
/*
* allocate a minimum of 1 page (4KB) worth of patch space, this is 512 entries
@@ -127,7 +128,7 @@ struct nvgpu_gr_ctx {
#endif
u64 global_ctx_buffer_va[NVGPU_GR_CTX_VA_COUNT];
int global_ctx_buffer_index[NVGPU_GR_CTX_VA_COUNT];
enum nvgpu_gr_global_ctx_index global_ctx_buffer_index[NVGPU_GR_CTX_VA_COUNT];
bool global_ctx_buffer_mapped;
u32 tsgid;