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gpu: nvgpu: Add doxygen documentation in pbdma_status.h

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JIRA NVGPU-3592

Change-Id: I8ac6d79327b2c11cf68ca052bc8f9d4fd078564a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2131132
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seema Khowala
2019-06-05 14:23:29 -07:00
committed by mobile promotions
parent 4a2188e34e
commit f3518ec5da
1 changed files with 84 additions and 2 deletions
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86
drivers/gpu/nvgpu/include/nvgpu/pbdma_status.h
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@@ -24,7 +24,11 @@
#define NVGPU_PBDMA_STATUS_H
#include <nvgpu/types.h>
/**
* @file
*
* Abstract interface for interpreting pbdma status info read from h/w.
*/
#define PBDMA_STATUS_ID_TYPE_CHID 0U
#define PBDMA_STATUS_ID_TYPE_TSGID 1U
#define PBDMA_STATUS_ID_TYPE_INVALID (~U32(0U))
@@ -37,34 +41,112 @@
#define PBDMA_STATUS_NEXT_ID_INVALID PBDMA_STATUS_ID_INVALID
enum nvgpu_pbdma_status_chsw_status {
/** Channel is not loaded on pbdma. Both id and next_id are invalid */
NVGPU_PBDMA_CHSW_STATUS_INVALID,
/**
* Channel is loaded on the pbdma. id field of pbdma_status
* h/w register is valid but next_id is not valid. Also host
* is currently not channel switching this pbdma.
*/
NVGPU_PBDMA_CHSW_STATUS_VALID,
/**
* Host is loading a new channel and the previous channel is
* invalid. In this state only next_id is valid.
*/
NVGPU_PBDMA_CHSW_STATUS_LOAD,
/**
* Host is saving the current channel and not loading a new one.
* In this state only id is valid.
*/
NVGPU_PBDMA_CHSW_STATUS_SAVE,
/**
* Host is switching between two valid channels. In this state both
* id and next_id are valid.
*/
NVGPU_PBDMA_CHSW_STATUS_SWITCH,
};
struct nvgpu_pbdma_status_info {
/** Pbdma_status h/w register's read value. */
u32 pbdma_reg_status;
/** Chan_status field of pbdma_status h/w register. */
u32 pbdma_channel_status;
/** Channel or tsg id of the context currently loaded on the pbdma. */
u32 id;
/** Specifies whether id is of channel or tsg type. */
u32 id_type;
/** Channel or tsg id of the next context to be loaded on the pbdma. */
u32 next_id;
/** Specifies whether next id is of channel or tsg type. */
u32 next_id_type;
/** Enum for chan_status field of pbdma_status h/w register. */
enum nvgpu_pbdma_status_chsw_status chsw_status;
};
/**
* nvgpu_pbdma_status_is_chsw_switch - Check if chsw_status is set to switch.
*
* @param pbdma_status - Pointer to struct containing pbdma_status h/w
* reg/field value.
*
* This interprets #pbdma_status and returns true if channel
* status is set to #NVGPU_PBDMA_CHSW_STATUS_SWITCH.
*/
bool nvgpu_pbdma_status_is_chsw_switch(struct nvgpu_pbdma_status_info
*pbdma_status);
/**
* nvgpu_pbdma_status_is_chsw_load - Check if chsw_status is set to load.
*
* @param pbdma_status - Pointer to struct containing pbdma_status h/w
* reg/field value.
*
* This interprets #pbdma_status and returns true if channel
* status is set to #NVGPU_PBDMA_CHSW_STATUS_LOAD.
*/
bool nvgpu_pbdma_status_is_chsw_load(struct nvgpu_pbdma_status_info
*pbdma_status);
/**
* nvgpu_pbdma_status_is_chsw_save - Check if chsw_status is set to save.
*
* @param pbdma_status - Pointer to struct containing pbdma_status h/w
* reg/field value.
*
* This interprets #pbdma_status and returns true if channel
* status is set to #NVGPU_PBDMA_CHSW_STATUS_SAVE.
*/
bool nvgpu_pbdma_status_is_chsw_save(struct nvgpu_pbdma_status_info
*pbdma_status);
/**
* nvgpu_pbdma_status_is_chsw_valid - Check if chsw_status is set to valid.
*
* @param pbdma_status - Pointer to struct containing pbdma_status h/w
* reg/field value.
*
* This interprets #pbdma_status and returns true if channel
* status is set to #NVGPU_PBDMA_CHSW_STATUS_VALID.
*/
bool nvgpu_pbdma_status_is_chsw_valid(struct nvgpu_pbdma_status_info
*pbdma_status);
/**
* nvgpu_pbdma_status_is_id_type_tsg - Check if id_type is tsg.
*
* @param pbdma_status - Pointer to struct containing pbdma_status h/w
* reg/field value.
*
* This interprets #pbdma_status and returns true if id_type
* is #PBDMA_STATUS_ID_TYPE_TSGID.
*/
bool nvgpu_pbdma_status_is_id_type_tsg(struct nvgpu_pbdma_status_info
*pbdma_status);
/**
* nvgpu_pbdma_status_is_next_id_type_tsg - Check if next_id_type is tsg.
*
* @param pbdma_status - Pointer to struct containing pbdma_status h/w
* reg/field value.
*
* This interprets #pbdma_status and returns true if next_id_type
* is #PBDMA_STATUS_NEXT_ID_TYPE_TSGID.
*/
bool nvgpu_pbdma_status_is_next_id_type_tsg(struct nvgpu_pbdma_status_info
*pbdma_status);