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gpu: nvgpu: gv11b: update code to HW CL 36758735

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Update headers and corresponding code to work with
HW CL # 36758735

Bug 1735760

Change-Id: Ie26bfaa6377ab797c5ad978e4796a55334761b5d
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1175882
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
This commit is contained in:
seshendra Gadagottu
2016-07-05 13:55:46 -07:00
committed by Terje Bergstrom
parent ca9cb97154
commit f4035d17a3
18 changed files with 1097 additions and 416 deletions
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43
drivers/gpu/nvgpu/gv11b/gr_gv11b.c
View File

@@ -911,17 +911,6 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm,
ctxsw_prog_main_image_magic_value_o()),
ctxsw_prog_main_image_magic_value_v_value_v());
gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n",
gk20a_mem_rd(g, mem,
ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o()));
gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n",
gk20a_mem_rd(g, mem,
ctxsw_prog_main_image_context_timestamp_buffer_ptr_o()));
gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n",
gk20a_mem_rd(g, mem,
ctxsw_prog_main_image_context_timestamp_buffer_control_o()));
gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n",
gk20a_mem_rd(g, mem,
@@ -1144,8 +1133,8 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g,
gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n",
gk20a_readl(g, gr_cwd_fs_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n",
gk20a_readl(g, gr_fe_tpc_fs_r(0)));
gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID(0): 0x%x\n",
gk20a_readl(g, gr_fe_tpc_fs_r()));
gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n",
gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0)));
gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n",
gk20a_readl(g, gr_cwd_sm_id_r(0)));
@@ -1552,16 +1541,16 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
gpc, tpc, global_esr);
if (cilp_enabled && sm_debugger_attached) {
if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f())
gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset,
gr_gpc0_tpc0_sm1_hww_global_esr_bpt_int_pending_f());
if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f())
gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f());
if (global_esr & gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f())
gk20a_writel(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset,
gr_gpc0_tpc0_sm1_hww_global_esr_single_step_complete_pending_f());
if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f())
gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset,
gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f());
global_mask = gr_gpcs_tpcs_sm1_hww_global_esr_multiple_warp_errors_pending_f() |
gr_gpcs_tpcs_sm1_hww_global_esr_bpt_pause_pending_f();
global_mask = gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() |
gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f();
if (warp_esr != 0 || (global_esr & global_mask) != 0) {
*ignore_debugger = true;
@@ -1585,7 +1574,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
}
/* reset the HWW errors after locking down */
global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm1_hww_global_esr_r() + offset);
global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset);
gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy);
gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
"CILP: HWWs cleared for gpc %d tpc %d\n",
@@ -1598,7 +1587,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
return ret;
}
dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset);
dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset);
if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) {
gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
"CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n",
@@ -1606,7 +1595,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
dbgr_control0 = set_field(dbgr_control0,
gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(),
gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f());
gk20a_writel(g, gr_gpc0_tpc0_sm1_dbgr_control0_r() + offset, dbgr_control0);
gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0);
}
gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg,
@@ -1720,10 +1709,10 @@ clean_up:
static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr)
{
if (!(hww_warp_esr & gr_gpc0_tpc0_sm1_hww_warp_esr_addr_valid_m()))
if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m()))
hww_warp_esr = set_field(hww_warp_esr,
gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_m(),
gr_gpc0_tpc0_sm1_hww_warp_esr_addr_error_type_none_f());
gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(),
gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f());
return hww_warp_esr;
}

76
drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h
View File

@@ -50,30 +50,6 @@
#ifndef _hw_bus_gv11b_h_
#define _hw_bus_gv11b_h_
static inline u32 bus_bar0_window_r(void)
{
return 0x00001700;
}
static inline u32 bus_bar0_window_base_f(u32 v)
{
return (v & 0xffffff) << 0;
}
static inline u32 bus_bar0_window_target_vid_mem_f(void)
{
return 0x0;
}
static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
{
return 0x2000000;
}
static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
{
return 0x3000000;
}
static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
{
return 0x00000010;
}
static inline u32 bus_bar1_block_r(void)
{
return 0x00001704;
@@ -130,6 +106,58 @@ static inline u32 bus_bar2_block_ptr_shift_v(void)
{
return 0x0000000c;
}
static inline u32 bus_bind_status_r(void)
{
return 0x00001710;
}
static inline u32 bus_bind_status_bar1_pending_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 bus_bind_status_bar1_pending_empty_f(void)
{
return 0x0;
}
static inline u32 bus_bind_status_bar1_pending_busy_f(void)
{
return 0x1;
}
static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
{
return (r >> 1) & 0x1;
}
static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
{
return 0x0;
}
static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
{
return 0x2;
}
static inline u32 bus_bind_status_bar2_pending_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 bus_bind_status_bar2_pending_empty_f(void)
{
return 0x0;
}
static inline u32 bus_bind_status_bar2_pending_busy_f(void)
{
return 0x4;
}
static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
{
return (r >> 3) & 0x1;
}
static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
{
return 0x0;
}
static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
{
return 0x8;
}
static inline u32 bus_intr_0_r(void)
{
return 0x00001100;

4
drivers/gpu/nvgpu/gv11b/hw_ccsr_gv11b.h
View File

@@ -56,7 +56,7 @@ static inline u32 ccsr_channel_inst_r(u32 i)
}
static inline u32 ccsr_channel_inst__size_1_v(void)
{
return 0x00001000;
return 0x00000200;
}
static inline u32 ccsr_channel_inst_ptr_f(u32 v)
{
@@ -88,7 +88,7 @@ static inline u32 ccsr_channel_r(u32 i)
}
static inline u32 ccsr_channel__size_1_v(void)
{
return 0x00001000;
return 0x00000200;
}
static inline u32 ccsr_channel_enable_v(u32 r)
{

164
drivers/gpu/nvgpu/gv11b/hw_ctxsw_prog_gv11b.h
View File

@@ -290,168 +290,4 @@ static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_
{
return 0x2;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void)
{
return 0x000000ac;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v)
{
return (v & 0xffff) << 0;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void)
{
return 0x000000b0;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void)
{
return 0x1ffff << 0;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void)
{
return 0x000000b4;
}
static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v)
{
return (v & 0xffffffff) << 0;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void)
{
return 0x00000080;
}
static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void)
{
return 0x00000020;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void)
{
return 0x00000000;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void)
{
return 0x00000000;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void)
{
return 0x00000004;
}
static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void)
{
return 0x600dbeef;
}
static inline u32 ctxsw_prog_record_timestamp_context_id_o(void)
{
return 0x00000008;
}
static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void)
{
return 0x0000000c;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void)
{
return 0x00000018;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void)
{
return 0x0000001c;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v)
{
return (v & 0xffffff) << 0;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r)
{
return (r >> 0) & 0xffffff;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v)
{
return (v & 0xff) << 24;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void)
{
return 0xff << 24;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r)
{
return (r >> 24) & 0xff;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void)
{
return 0x00000001;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void)
{
return 0x1000000;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void)
{
return 0x00000002;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void)
{
return 0x2000000;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void)
{
return 0x0000000a;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void)
{
return 0xa000000;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void)
{
return 0x0000000b;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void)
{
return 0xb000000;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void)
{
return 0x0000000c;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void)
{
return 0xc000000;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void)
{
return 0x0000000d;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void)
{
return 0xd000000;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void)
{
return 0x00000003;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void)
{
return 0x3000000;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void)
{
return 0x00000004;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void)
{
return 0x4000000;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void)
{
return 0x00000005;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void)
{
return 0x5000000;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void)
{
return 0x000000ff;
}
static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void)
{
return 0xff000000;
}
#endif

8
drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h
View File

@@ -182,6 +182,10 @@ static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
{
return 0x20;
}
static inline u32 fb_mmu_invalidate_replay_cancel_f(void)
{
return 0x20;
}
static inline u32 fb_mmu_invalidate_sys_membar_s(void)
{
return 1;
@@ -470,4 +474,8 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
{
return 0x00000001;
}
static inline u32 fb_niso_flush_sysmem_addr_r(void)
{
return 0x00100c10;
}
#endif

20
drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h
View File

@@ -104,7 +104,7 @@ static inline u32 fifo_eng_runlist_base_r(u32 i)
}
static inline u32 fifo_eng_runlist_base__size_1_v(void)
{
return 0x0000000d;
return 0x00000001;
}
static inline u32 fifo_eng_runlist_r(u32 i)
{
@@ -112,7 +112,7 @@ static inline u32 fifo_eng_runlist_r(u32 i)
}
static inline u32 fifo_eng_runlist__size_1_v(void)
{
return 0x0000000d;
return 0x00000001;
}
static inline u32 fifo_eng_runlist_length_f(u32 v)
{
@@ -268,7 +268,7 @@ static inline u32 fifo_intr_mmu_fault_id_r(void)
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void)
{
return 0x00000040;
return 0x00000000;
}
static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void)
{
@@ -332,7 +332,7 @@ static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
}
static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
{
return 0x0000000e;
return 0x00000001;
}
static inline u32 fifo_intr_runlist_r(void)
{
@@ -412,7 +412,7 @@ static inline u32 fifo_engine_status_r(u32 i)
}
static inline u32 fifo_engine_status__size_1_v(void)
{
return 0x0000000f;
return 0x00000002;
}
static inline u32 fifo_engine_status_id_v(u32 r)
{
@@ -500,7 +500,7 @@ static inline u32 fifo_pbdma_status_r(u32 i)
}
static inline u32 fifo_pbdma_status__size_1_v(void)
{
return 0x0000000e;
return 0x00000001;
}
static inline u32 fifo_pbdma_status_id_v(u32 r)
{
@@ -600,11 +600,11 @@ static inline u32 fifo_replay_fault_buffer_size_r(void)
}
static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v)
{
return (v & 0x3fff) << 0;
return (v & 0x1ff) << 0;
}
static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void)
{
return 0x00002000;
return 0x000000c0;
}
static inline u32 fifo_replay_fault_buffer_get_r(void)
{
@@ -612,7 +612,7 @@ static inline u32 fifo_replay_fault_buffer_get_r(void)
}
static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v)
{
return (v & 0x3fff) << 0;
return (v & 0x1ff) << 0;
}
static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void)
{
@@ -624,7 +624,7 @@ static inline u32 fifo_replay_fault_buffer_put_r(void)
}
static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v)
{
return (v & 0x3fff) << 0;
return (v & 0x1ff) << 0;
}
static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void)
{

2
drivers/gpu/nvgpu/gv11b/hw_fuse_gv11b.h
View File

@@ -124,7 +124,7 @@ static inline u32 fuse_status_opt_fbp_r(void)
}
static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
{
return (r >> (0 + i*0)) & 0x1;
return (r >> (0 + i*1)) & 0x1;
}
static inline u32 fuse_opt_ecc_en_r(void)
{

42
drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h
View File

@@ -70,9 +70,17 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
{
return 0x2;
}
static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
{
return 0x4;
}
static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
{
return 0x6;
}
static inline u32 gmmu_new_pde_address_sys_f(u32 v)
{
return (v & 0xfffffff) << 8;
return (v & 0xffffff) << 8;
}
static inline u32 gmmu_new_pde_address_sys_w(void)
{
@@ -118,6 +126,14 @@ static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
{
return 0x2;
}
static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
{
return 0x4;
}
static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
{
return 0x6;
}
static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
{
return (v & 0xfffffff) << 4;
@@ -138,6 +154,14 @@ static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
{
return 0x2;
}
static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
{
return 0x4;
}
static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
{
return 0x6;
}
static inline u32 gmmu_new_dual_pde_vol_small_w(void)
{
return 2;
@@ -164,7 +188,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
}
static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
{
return (v & 0xfffffff) << 8;
return (v & 0xffffff) << 8;
}
static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
{
@@ -212,7 +236,7 @@ static inline u32 gmmu_new_pte_privilege_false_f(void)
}
static inline u32 gmmu_new_pte_address_sys_f(u32 v)
{
return (v & 0xfffffff) << 8;
return (v & 0xffffff) << 8;
}
static inline u32 gmmu_new_pte_address_sys_w(void)
{
@@ -238,6 +262,14 @@ static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
{
return 0x0;
}
static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
{
return 0x4;
}
static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
{
return 0x6;
}
static inline u32 gmmu_new_pte_read_only_w(void)
{
return 0;
@@ -1078,7 +1110,7 @@ static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void)
{
return 0x000000de;
}
static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void)
static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void)
{
return 0x000000cc;
}
@@ -1142,7 +1174,7 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void)
{
return 0x000000ec;
}
static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void)
static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void)
{
return 0x000000cd;
}

802
drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h
View File

File diff suppressed because it is too large Load Diff

28
drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h
View File

@@ -50,6 +50,26 @@
#ifndef _hw_ltc_gv11b_h_
#define _hw_ltc_gv11b_h_
static inline u32 ltc_pltcg_base_v(void)
{
return 0x00140000;
}
static inline u32 ltc_pltcg_extent_v(void)
{
return 0x0017ffff;
}
static inline u32 ltc_ltc0_ltss_v(void)
{
return 0x00140200;
}
static inline u32 ltc_ltc0_lts0_v(void)
{
return 0x00140400;
}
static inline u32 ltc_ltcs_ltss_v(void)
{
return 0x0017e200;
}
static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
{
return 0x0014046c;
@@ -550,4 +570,12 @@ static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
{
return (r >> 16) & 0x1f;
}
static inline u32 ltc_ltca_g_axi_pctrl_r(void)
{
return 0x00160000;
}
static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v)
{
return (v & 0xff) << 2;
}
#endif

4
drivers/gpu/nvgpu/gv11b/hw_mc_gv11b.h
View File

@@ -78,10 +78,6 @@ static inline u32 mc_intr_pfifo_pending_f(void)
{
return 0x100;
}
static inline u32 mc_intr_hub_pending_f(void)
{
return 0x200;
}
static inline u32 mc_intr_pgraph_pending_f(void)
{
return 0x1000;

74
drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h
View File

@@ -72,7 +72,7 @@ static inline u32 pbdma_gp_base_r(u32 i)
}
static inline u32 pbdma_gp_base__size_1_v(void)
{
return 0x0000000e;
return 0x00000001;
}
static inline u32 pbdma_gp_base_offset_f(u32 v)
{
@@ -334,6 +334,38 @@ static inline u32 pbdma_userd_addr_f(u32 v)
{
return (v & 0x7fffff) << 9;
}
static inline u32 pbdma_config_r(u32 i)
{
return 0x000400f4 + i*8192;
}
static inline u32 pbdma_config_l2_evict_first_f(void)
{
return 0x0;
}
static inline u32 pbdma_config_l2_evict_normal_f(void)
{
return 0x1;
}
static inline u32 pbdma_config_l2_evict_last_f(void)
{
return 0x2;
}
static inline u32 pbdma_config_ce_split_enable_f(void)
{
return 0x0;
}
static inline u32 pbdma_config_ce_split_disable_f(void)
{
return 0x10;
}
static inline u32 pbdma_config_auth_level_non_privileged_f(void)
{
return 0x0;
}
static inline u32 pbdma_config_auth_level_privileged_f(void)
{
return 0x100;
}
static inline u32 pbdma_userd_hi_r(u32 i)
{
return 0x0004000c + i*8192;
@@ -478,6 +510,14 @@ static inline u32 pbdma_intr_0_signature_pending_f(void)
{
return 0x80000000;
}
static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void)
{
return 0x10000000;
}
static inline u32 pbdma_intr_1_r(u32 i)
{
return 0x00040148 + i*8192;
}
static inline u32 pbdma_intr_en_0_r(u32 i)
{
return 0x0004010c + i*8192;
@@ -526,6 +566,38 @@ static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v)
{
return (v & 0x7fff) << 0;
}
static inline u32 pbdma_syncpointa_r(u32 i)
{
return 0x000400a4 + i*8192;
}
static inline u32 pbdma_syncpointa_payload_v(u32 r)
{
return (r >> 0) & 0xffffffff;
}
static inline u32 pbdma_syncpointb_r(u32 i)
{
return 0x000400a8 + i*8192;
}
static inline u32 pbdma_syncpointb_op_v(u32 r)
{
return (r >> 0) & 0x1;
}
static inline u32 pbdma_syncpointb_op_wait_v(void)
{
return 0x00000000;
}
static inline u32 pbdma_syncpointb_wait_switch_v(u32 r)
{
return (r >> 4) & 0x1;
}
static inline u32 pbdma_syncpointb_wait_switch_en_v(void)
{
return 0x00000001;
}
static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r)
{
return (r >> 8) & 0xfff;
}
static inline u32 pbdma_runlist_timeslice_r(u32 i)
{
return 0x000400f8 + i*8192;

16
drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h
View File

@@ -52,7 +52,7 @@
static inline u32 perf_pmasys_control_r(void)
{
return 0x0024a000;
return 0x001b4000;
}
static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
{
@@ -84,7 +84,7 @@ static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
}
static inline u32 perf_pmasys_mem_block_r(void)
{
return 0x0024a070;
return 0x001b4070;
}
static inline u32 perf_pmasys_mem_block_base_f(u32 v)
{
@@ -148,7 +148,7 @@ static inline u32 perf_pmasys_mem_block_valid_false_f(void)
}
static inline u32 perf_pmasys_outbase_r(void)
{
return 0x0024a074;
return 0x001b4074;
}
static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
{
@@ -156,7 +156,7 @@ static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
}
static inline u32 perf_pmasys_outbaseupper_r(void)
{
return 0x0024a078;
return 0x001b4078;
}
static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
{
@@ -164,7 +164,7 @@ static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
}
static inline u32 perf_pmasys_outsize_r(void)
{
return 0x0024a07c;
return 0x001b407c;
}
static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
{
@@ -172,7 +172,7 @@ static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
}
static inline u32 perf_pmasys_mem_bytes_r(void)
{
return 0x0024a084;
return 0x001b4084;
}
static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
{
@@ -180,7 +180,7 @@ static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
}
static inline u32 perf_pmasys_mem_bump_r(void)
{
return 0x0024a088;
return 0x001b4088;
}
static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
{
@@ -188,7 +188,7 @@ static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
}
static inline u32 perf_pmasys_enginestatus_r(void)
{
return 0x0024a0a4;
return 0x001b40a4;
}
static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
{

24
drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h
View File

@@ -70,6 +70,10 @@ static inline u32 proj_lts_stride_v(void)
{
return 0x00000200;
}
static inline u32 proj_fbpa_stride_v(void)
{
return 0x00004000;
}
static inline u32 proj_ppc_in_gpc_base_v(void)
{
return 0x00003000;
@@ -102,29 +106,37 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void)
{
return 0x00001800;
}
static inline u32 proj_host_num_engines_v(void)
{
return 0x00000002;
}
static inline u32 proj_host_num_pbdma_v(void)
{
return 0x0000000e;
return 0x00000001;
}
static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
{
return 0x00000007;
return 0x00000002;
}
static inline u32 proj_scal_litter_num_fbps_v(void)
{
return 0x00000008;
return 0x00000001;
}
static inline u32 proj_scal_litter_num_fbpas_v(void)
{
return 0x00000001;
}
static inline u32 proj_scal_litter_num_gpcs_v(void)
{
return 0x00000008;
return 0x00000001;
}
static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
{
return 0x00000003;
return 0x00000001;
}
static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
{
return 0x00000003;
return 0x00000002;
}
static inline u32 proj_scal_litter_num_zcull_banks_v(void)
{

4
drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h
View File

@@ -542,6 +542,10 @@ static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
{
return 0x20000000;
}
static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
{
return 0x30000000;
}
static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
{
return (v & 0x1) << 30;

42
drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h
View File

@@ -148,7 +148,7 @@ static inline u32 ram_in_page_dir_base_lo_w(void)
}
static inline u32 ram_in_page_dir_base_hi_f(u32 v)
{
return (v & 0xffffffff) << 0;
return (v & 0xff) << 0;
}
static inline u32 ram_in_page_dir_base_hi_w(void)
{
@@ -354,6 +354,14 @@ static inline u32 ram_fc_allowed_syncpoints_w(void)
{
return 58;
}
static inline u32 ram_fc_syncpointa_w(void)
{
return 41;
}
static inline u32 ram_fc_syncpointb_w(void)
{
return 42;
}
static inline u32 ram_fc_target_w(void)
{
return 43;
@@ -436,7 +444,11 @@ static inline u32 ram_userd_gp_top_level_get_hi_w(void)
}
static inline u32 ram_rl_entry_size_v(void)
{
return 0x00000010;
return 0x00000008;
}
static inline u32 ram_rl_entry_chid_f(u32 v)
{
return (v & 0xfff) << 0;
}
static inline u32 ram_rl_entry_id_f(u32 v)
{
@@ -444,14 +456,34 @@ static inline u32 ram_rl_entry_id_f(u32 v)
}
static inline u32 ram_rl_entry_type_f(u32 v)
{
return (v & 0x1) << 0;
return (v & 0x1) << 13;
}
static inline u32 ram_rl_entry_type_chid_f(void)
{
return 0x0;
}
static inline u32 ram_rl_entry_type_tsg_f(void)
{
return 0x1;
return 0x2000;
}
static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
{
return (v & 0xf) << 14;
}
static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
{
return 0xc000;
}
static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
{
return (v & 0xff) << 18;
}
static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
{
return 0x2000000;
}
static inline u32 ram_rl_entry_tsg_length_f(u32 v)
{
return (v & 0xff) << 0;
return (v & 0x3f) << 26;
}
#endif

124
drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h
View File

@@ -54,6 +54,114 @@ static inline u32 therm_use_a_r(void)
{
return 0x00020798;
}
static inline u32 therm_use_a_ext_therm_0_enable_f(void)
{
return 0x1;
}
static inline u32 therm_use_a_ext_therm_1_enable_f(void)
{
return 0x2;
}
static inline u32 therm_use_a_ext_therm_2_enable_f(void)
{
return 0x4;
}
static inline u32 therm_evt_ext_therm_0_r(void)
{
return 0x00020700;
}
static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v)
{
return (v & 0x3f) << 24;
}
static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void)
{
return 0x00000001;
}
static inline u32 therm_evt_ext_therm_0_mode_f(u32 v)
{
return (v & 0x3) << 30;
}
static inline u32 therm_evt_ext_therm_0_mode_normal_v(void)
{
return 0x00000000;
}
static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void)
{
return 0x00000001;
}
static inline u32 therm_evt_ext_therm_0_mode_forced_v(void)
{
return 0x00000002;
}
static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void)
{
return 0x00000003;
}
static inline u32 therm_evt_ext_therm_1_r(void)
{
return 0x00020704;
}
static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v)
{
return (v & 0x3f) << 24;
}
static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void)
{
return 0x00000002;
}
static inline u32 therm_evt_ext_therm_1_mode_f(u32 v)
{
return (v & 0x3) << 30;
}
static inline u32 therm_evt_ext_therm_1_mode_normal_v(void)
{
return 0x00000000;
}
static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void)
{
return 0x00000001;
}
static inline u32 therm_evt_ext_therm_1_mode_forced_v(void)
{
return 0x00000002;
}
static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void)
{
return 0x00000003;
}
static inline u32 therm_evt_ext_therm_2_r(void)
{
return 0x00020708;
}
static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v)
{
return (v & 0x3f) << 24;
}
static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void)
{
return 0x00000003;
}
static inline u32 therm_evt_ext_therm_2_mode_f(u32 v)
{
return (v & 0x3) << 30;
}
static inline u32 therm_evt_ext_therm_2_mode_normal_v(void)
{
return 0x00000000;
}
static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void)
{
return 0x00000001;
}
static inline u32 therm_evt_ext_therm_2_mode_forced_v(void)
{
return 0x00000002;
}
static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void)
{
return 0x00000003;
}
static inline u32 therm_weight_1_r(void)
{
return 0x00020024;
@@ -106,6 +214,22 @@ static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
{
return 0x4;
}
static inline u32 therm_gate_ctrl_eng_pwr_m(void)
{
return 0x3 << 4;
}
static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void)
{
return 0x10;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_v(void)
{
return 0x00000002;
}
static inline u32 therm_gate_ctrl_eng_pwr_off_f(void)
{
return 0x20;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
{
return (v & 0x1f) << 8;

36
drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h
View File

@@ -138,13 +138,37 @@ static inline u32 top_device_info_type_enum_graphics_f(void)
{
return 0x0;
}
static inline u32 top_device_info_type_enum_copy0_v(void)
static inline u32 top_device_info_type_enum_copy2_v(void)
{
return 0x00000001;
return 0x00000003;
}
static inline u32 top_device_info_type_enum_copy0_f(void)
static inline u32 top_device_info_type_enum_copy2_f(void)
{
return 0x4;
return 0xc;
}
static inline u32 top_device_info_type_enum_lce_v(void)
{
return 0x00000013;
}
static inline u32 top_device_info_type_enum_lce_f(void)
{
return 0x4c;
}
static inline u32 top_device_info_engine_v(u32 r)
{
return (r >> 5) & 0x1;
}
static inline u32 top_device_info_runlist_v(u32 r)
{
return (r >> 4) & 0x1;
}
static inline u32 top_device_info_intr_v(u32 r)
{
return (r >> 3) & 0x1;
}
static inline u32 top_device_info_reset_v(u32 r)
{
return (r >> 2) & 0x1;
}
static inline u32 top_device_info_entry_v(u32 r)
{
@@ -158,10 +182,6 @@ static inline u32 top_device_info_entry_enum_v(void)
{
return 0x00000002;
}
static inline u32 top_device_info_entry_engine_type_v(void)
{
return 0x00000002;
}
static inline u32 top_device_info_entry_data_v(void)
{
return 0x00000001;