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gpu: nvgpu: add ioctl to configure l2 max_ways_evict_last
Add ioctl support to configure and read the max number of lines/ways in a L2 cache set that can be marked as EVICT_LAST. This is accomplished through two new ltc hals: set_l2_max_ways_evict_last, get_l2_max_ways_evict_last. These hals will only be set for nvgpu-next chips. Incase of legacy chips, the IOCTLs will return error -ENOSYS. Generate following litter constants to get the number of sets in a l2 slice and the number of ways in each set: - GPU_LIT_NUM_LTC_LTS_SETS - GPU_LIT_NUM_LTC_LTS_WAYS Add gpu characteritics flag: NVGPU_L2_MAX_WAYS_EVICT_LAST_ENABLED to allow userspace driver to determine if L2_MAX_WAYS_EVICT_LAST ioctl is supported. Bug 200605474 Change-Id: Id3180f891399f5e128500f3835d762aee59953e0 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2445884 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -184,6 +184,8 @@ struct nvgpu_gpu_zbc_query_table_args {
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#define NVGPU_GPU_FLAGS_SUPPORT_GET_GR_CONTEXT (1ULL << 49)
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/* Additional buffer metadata association supported */
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#define NVGPU_GPU_FLAGS_SUPPORT_BUFFER_METADATA (1ULL << 50)
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/* Flag to indicate whether configuring L2_MAXEVICTLAST_WAYS is supported */
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#define NVGPU_GPU_FLAGS_L2_MAX_WAYS_EVICT_LAST_ENABLED (1ULL << 51)
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/* SM LRF ECC is enabled */
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#define NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF (1ULL << 60)
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/* SM SHM ECC is enabled */
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@@ -72,6 +72,18 @@ struct nvgpu_tsg_read_single_sm_error_state_args {
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__u64 record_size;
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};
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/*
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* This struct is used to read and configure l2 max evict_last
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* setting.
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*/
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struct nvgpu_tsg_l2_max_ways_evict_last_args {
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/*
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* Maximum number of ways in a l2 cache set that can be allocated
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* with eviction_policy=EVICT_LAST
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*/
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__u32 max_ways;
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};
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#define NVGPU_TSG_IOCTL_BIND_CHANNEL \
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_IOW(NVGPU_TSG_IOCTL_MAGIC, 1, int)
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#define NVGPU_TSG_IOCTL_UNBIND_CHANNEL \
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@@ -95,10 +107,17 @@ struct nvgpu_tsg_read_single_sm_error_state_args {
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#define NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE \
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_IOWR(NVGPU_TSG_IOCTL_MAGIC, 12, \
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struct nvgpu_tsg_read_single_sm_error_state_args)
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#define NVGPU_TSG_IOCTL_SET_L2_MAX_WAYS_EVICT_LAST \
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_IOW(NVGPU_TSG_IOCTL_MAGIC, 13, \
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struct nvgpu_tsg_l2_max_ways_evict_last_args)
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#define NVGPU_TSG_IOCTL_GET_L2_MAX_WAYS_EVICT_LAST \
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_IOR(NVGPU_TSG_IOCTL_MAGIC, 14, \
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struct nvgpu_tsg_l2_max_ways_evict_last_args)
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#define NVGPU_TSG_IOCTL_MAX_ARG_SIZE \
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sizeof(struct nvgpu_tsg_bind_channel_ex_args)
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#define NVGPU_TSG_IOCTL_LAST \
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_IOC_NR(NVGPU_TSG_IOCTL_READ_SINGLE_SM_ERROR_STATE)
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_IOC_NR(NVGPU_TSG_IOCTL_GET_L2_MAX_WAYS_EVICT_LAST)
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/*
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* /dev/nvhost-dbg-gpu device
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