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gpu: nvgpu: Fix CERT INT30-C errors in hal.gr.init unit

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Fix CERT INT30-C erros in hal.gr.init units.
Unsigned integer operation may wrap. Use safe_ops macro to fix
the wrap errors.

Jira NVGPU-3585

Change-Id: I1c825decfbfba52136aef55c791e3d328a3470a2
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2132617
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-06-07 15:52:41 -07:00
committed by mobile promotions
parent 0c13e9e8ad
commit f4b8feccf5
3 changed files with 49 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
View File

@@ -466,25 +466,32 @@ void gm20b_gr_init_pd_tpc_per_gpc(struct gk20a *g,
tpc_per_gpc =
gr_pd_num_tpc_per_gpc_count0_f(
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_id + 0U)) |
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_id)) |
gr_pd_num_tpc_per_gpc_count1_f(
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_id + 1U)) |
nvgpu_gr_config_get_gpc_tpc_count(gr_config,
nvgpu_safe_add_u32(gpc_id, 1U))) |
gr_pd_num_tpc_per_gpc_count2_f(
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_id + 2U)) |
nvgpu_gr_config_get_gpc_tpc_count(gr_config,
nvgpu_safe_add_u32(gpc_id, 2U))) |
gr_pd_num_tpc_per_gpc_count3_f(
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_id + 3U)) |
nvgpu_gr_config_get_gpc_tpc_count(gr_config,
nvgpu_safe_add_u32(gpc_id, 3U))) |
gr_pd_num_tpc_per_gpc_count4_f(
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_id + 4U)) |
nvgpu_gr_config_get_gpc_tpc_count(gr_config,
nvgpu_safe_add_u32(gpc_id, 4U))) |
gr_pd_num_tpc_per_gpc_count5_f(
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_id + 5U)) |
nvgpu_gr_config_get_gpc_tpc_count(gr_config,
nvgpu_safe_add_u32(gpc_id, 5U))) |
gr_pd_num_tpc_per_gpc_count6_f(
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_id + 6U)) |
nvgpu_gr_config_get_gpc_tpc_count(gr_config,
nvgpu_safe_add_u32(gpc_id, 6U))) |
gr_pd_num_tpc_per_gpc_count7_f(
nvgpu_gr_config_get_gpc_tpc_count(gr_config, gpc_id + 7U));
nvgpu_gr_config_get_gpc_tpc_count(gr_config,
nvgpu_safe_add_u32(gpc_id, 7U)));
nvgpu_writel(g, gr_pd_num_tpc_per_gpc_r(reg_index), tpc_per_gpc);
nvgpu_writel(g, gr_ds_num_tpc_per_gpc_r(reg_index), tpc_per_gpc);
gpc_id += 8U;
gpc_id = nvgpu_safe_add_u32(gpc_id, 8U);
}
}
@@ -867,11 +874,11 @@ u32 gm20b_gr_init_get_global_attr_cb_size(struct gk20a *g, u32 tpc_count,
gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(),
max_tpc));
size += nvgpu_safe_mult_u32(
size = nvgpu_safe_add_u32(size, nvgpu_safe_mult_u32(
g->ops.gr.init.get_alpha_cb_size(g, tpc_count),
nvgpu_safe_mult_u32(
gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(),
max_tpc));
max_tpc)));
return size;
}
@@ -1084,9 +1091,10 @@ void gm20b_gr_init_commit_global_cb_manager(struct gk20a *g,
sum_temp_pcc),
attrib_offset_in_chunk, patch);
attrib_offset_in_chunk +=
attrib_offset_in_chunk = nvgpu_safe_add_u32(
attrib_offset_in_chunk,
nvgpu_safe_mult_u32(attrib_cb_size,
pes_tpc_count);
pes_tpc_count));
nvgpu_gr_ctx_patch_write(g, gr_ctx,
nvgpu_safe_add_u32(
@@ -1100,9 +1108,10 @@ void gm20b_gr_init_commit_global_cb_manager(struct gk20a *g,
sum_temp_pcc),
alpha_offset_in_chunk, patch);
alpha_offset_in_chunk +=
alpha_offset_in_chunk = nvgpu_safe_add_u32(
alpha_offset_in_chunk,
nvgpu_safe_mult_u32(alpha_cb_size,
pes_tpc_count);
pes_tpc_count));
nvgpu_gr_ctx_patch_write(g, gr_ctx,
gr_gpcs_swdx_tc_beta_cb_size_r(

14
drivers/gpu/nvgpu/hal/gr/init/gr_init_gp10b.c
View File

@@ -301,11 +301,11 @@ u32 gp10b_gr_init_get_global_attr_cb_size(struct gk20a *g, u32 tpc_count,
gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(),
max_tpc));
size += nvgpu_safe_mult_u32(
size = nvgpu_safe_add_u32(size, nvgpu_safe_mult_u32(
g->ops.gr.init.get_alpha_cb_size(g, tpc_count),
nvgpu_safe_mult_u32(
gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(),
max_tpc));
max_tpc)));
size = ALIGN(size, 128);
@@ -532,9 +532,10 @@ void gp10b_gr_init_commit_global_cb_manager(struct gk20a *g,
sum_temp_pcc),
cbm_cfg_size_steadystate, patch);
attrib_offset_in_chunk +=
attrib_offset_in_chunk = nvgpu_safe_add_u32(
attrib_offset_in_chunk,
nvgpu_safe_mult_u32(attrib_size_in_chunk,
pes_tpc_count);
pes_tpc_count));
nvgpu_gr_ctx_patch_write(g, gr_ctx,
nvgpu_safe_add_u32(
@@ -548,9 +549,10 @@ void gp10b_gr_init_commit_global_cb_manager(struct gk20a *g,
sum_temp_pcc),
alpha_offset_in_chunk, patch);
alpha_offset_in_chunk +=
alpha_offset_in_chunk = nvgpu_safe_add_u32(
alpha_offset_in_chunk,
nvgpu_safe_mult_u32(alpha_cb_size,
pes_tpc_count);
pes_tpc_count));
nvgpu_gr_ctx_patch_write(g, gr_ctx,
gr_gpcs_swdx_tc_beta_cb_size_r(

29
drivers/gpu/nvgpu/hal/gr/init/gr_init_gv11b.c
View File

@@ -289,13 +289,14 @@ u32 gv11b_gr_init_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc,
BIT32(tpc)) != 0U) {
break;
}
tpc_new += nvgpu_gr_config_get_pes_tpc_count(gr_config,
gpc, pes);
tpc_new = nvgpu_safe_add_u32(tpc_new,
nvgpu_gr_config_get_pes_tpc_count(gr_config,
gpc, pes));
}
temp = nvgpu_safe_sub_u32(BIT32(tpc), 1U) &
nvgpu_gr_config_get_pes_tpc_mask(gr_config, gpc, pes);
temp = (u32)hweight32(temp);
tpc_new += temp;
tpc_new = nvgpu_safe_add_u32(tpc_new, temp);
nvgpu_log_info(g, "tpc: %d -> new tpc: %d", tpc, tpc_new);
return tpc_new;
@@ -742,11 +743,11 @@ u32 gv11b_gr_init_get_global_attr_cb_size(struct gk20a *g, u32 tpc_count,
gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(),
max_tpc));
size += nvgpu_safe_mult_u32(
size = nvgpu_safe_add_u32(size, nvgpu_safe_mult_u32(
g->ops.gr.init.get_alpha_cb_size(g, tpc_count),
nvgpu_safe_mult_u32(
gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(),
max_tpc));
max_tpc)));
size = ALIGN(size, 128);
@@ -920,36 +921,40 @@ u32 gv11b_gr_init_get_patch_slots(struct gk20a *g,
/*
* CMD to update PE table
*/
size++;
size = nvgpu_safe_add_u32(size, 1U);
/*
* Update PE table contents
* for PE table, each patch buffer update writes 32 TPCs
*/
size += DIV_ROUND_UP(nvgpu_gr_config_get_tpc_count(config), 32U);
size = nvgpu_safe_add_u32(size,
DIV_ROUND_UP(nvgpu_gr_config_get_tpc_count(config), 32U));
/*
* Update the PL table contents
* For PL table, each patch buffer update configures 4 TPCs
*/
size += DIV_ROUND_UP(nvgpu_gr_config_get_tpc_count(config), 4U);
size = nvgpu_safe_add_u32(size,
DIV_ROUND_UP(nvgpu_gr_config_get_tpc_count(config), 4U));
/*
* We need this for all subcontexts
*/
size *= g->ops.gr.init.get_max_subctx_count();
size = nvgpu_safe_mult_u32(size,
g->ops.gr.init.get_max_subctx_count());
/*
* Add space for a partition mode change as well
* reserve two slots since DYNAMIC -> STATIC requires
* DYNAMIC -> NONE -> STATIC
*/
size += 2U;
size = nvgpu_safe_add_u32(size, 2U);
/*
* Add current patch buffer size
*/
size += gm20b_gr_init_get_patch_slots(g, config);
size = nvgpu_safe_add_u32(size,
gm20b_gr_init_get_patch_slots(g, config));
/*
* Align to 4K size
@@ -959,7 +964,7 @@ u32 gv11b_gr_init_get_patch_slots(struct gk20a *g,
/*
* Increase the size to accommodate for additional TPC partition update
*/
size += nvgpu_safe_mult_u32(2U, slot_size);
size = nvgpu_safe_add_u32(size, nvgpu_safe_mult_u32(2U, slot_size));
return size;
}