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gpu: nvgpu: move gk20a_init_gr to common.gr.init

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Move gk20a_init_gr function from gr_gk20a.c to
gr.c as nvgpu_gr_init.
Update all files that call gk20a_init_gr function.

JIRA NVGPU-1885

Change-Id: I318a34778e23a7372be574ee9c21c5b65011e535
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2092648
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-04-08 11:34:28 -07:00
committed by mobile promotions
parent c99f13e842
commit f57d9f97c2
6 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/nvgpu/common/gr/gr.c
View File

@@ -51,6 +51,11 @@ u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc)
return tpc_offset;
}
void nvgpu_gr_init(struct gk20a *g)
{
nvgpu_cond_init(&g->gr.init_wq);
}
int nvgpu_gr_suspend(struct gk20a *g)
{
int ret = 0;

5
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
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@@ -2543,11 +2543,6 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch,
return err;
}
void gk20a_init_gr(struct gk20a *g)
{
nvgpu_cond_init(&g->gr.init_wq);
}
int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
u32 global_esr_mask, bool check_errors)
{

3
drivers/gpu/nvgpu/gk20a/gr_gk20a.h
View File

@@ -250,8 +250,6 @@ struct gpu_ops;
int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
struct channel_gk20a *c,
struct nvgpu_gr_ctx *gr_ctx);
void gk20a_init_gr(struct gk20a *g);
int gk20a_init_gr_channel(struct channel_gk20a *ch_gk20a);
int gk20a_gr_isr(struct gk20a *g);
@@ -304,7 +302,6 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch);
int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
bool *post_event, struct channel_gk20a *fault_ch,
u32 *hww_global_esr);
int gr_gk20a_init_ctx_state(struct gk20a *g);
#if defined(CONFIG_GK20A_CYCLE_STATS)
int gr_gk20a_css_attach(struct channel_gk20a *ch, /* in - main hw structure */

1
drivers/gpu/nvgpu/include/nvgpu/gr/gr.h
View File

@@ -33,5 +33,6 @@ u32 nvgpu_gr_tpc_offset(struct gk20a *g, u32 tpc);
int nvgpu_gr_suspend(struct gk20a *g);
void nvgpu_gr_flush_channel_tlb(struct gk20a *g);
void nvgpu_gr_wait_initialized(struct gk20a *g);
void nvgpu_gr_init(struct gk20a *g);
#endif /* NVGPU_GR_H */

3
drivers/gpu/nvgpu/os/linux/driver_common.c
View File

@@ -30,6 +30,7 @@
#include <nvgpu/sizes.h>
#include <nvgpu/gk20a.h>
#include <nvgpu/regops.h>
#include <nvgpu/gr/gr.h>
#include "platform_gk20a.h"
#include "module.h"
@@ -102,7 +103,7 @@ static void nvgpu_init_vars(struct gk20a *g)
static void nvgpu_init_gr_vars(struct gk20a *g)
{
gk20a_init_gr(g);
nvgpu_gr_init(g);
nvgpu_log_info(g, "total ram pages : %lu", totalram_pages);
g->max_comptag_mem = totalram_size_in_mb;

3
drivers/gpu/nvgpu/os/linux/vgpu/vgpu_linux.c
View File

@@ -34,6 +34,7 @@
#include <nvgpu/channel.h>
#include <nvgpu/regops.h>
#include <nvgpu/clk_arb.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/vgpu/os_init_hal_vgpu.h>
@@ -441,7 +442,7 @@ int vgpu_probe(struct platform_device *pdev)
nvgpu_atomic_set(&gk20a->timeouts_disabled_refcount, 0);
vgpu_create_sysfs(dev);
gk20a_init_gr(gk20a);
nvgpu_gr_init(gk20a);
nvgpu_log_info(gk20a, "total ram pages : %lu", totalram_pages);
gk20a->max_comptag_mem = totalram_size_in_mb;