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gpu: nvgpu: update nvgpu_(err/ecc) to support nvgpu-next errors
Update nvgpu_err and nvgpu_ecc units to support nvgpu-next errors. Jira NVGPU-5286 Change-Id: Iaa36c408a46aec163ba3e375bb7c363aa96bdc8d Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2407382 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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committed by
Alex Waterman
parent
db3764511b
commit
f5f9cd9cba
@@ -172,6 +172,9 @@ struct nvgpu_ecc {
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struct nvgpu_ecc_stat **sm_icache_ecc_corrected_err_count;
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/** SM icache uncorrected error count. */
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struct nvgpu_ecc_stat **sm_icache_ecc_uncorrected_err_count;
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#if defined(CONFIG_NVGPU_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
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#include "include/nvgpu/gr/nvgpu_next_gr_ecc.h"
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#endif
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/** GCC l1.5-cache corrected error count. */
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struct nvgpu_ecc_stat *gcc_l15_ecc_corrected_err_count;
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@@ -704,4 +704,8 @@ void nvgpu_report_mmu_err(struct gk20a *g, u32 hw_unit,
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void gr_intr_report_ctxsw_error(struct gk20a *g, u32 err_type, u32 chid,
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u32 mailbox_value);
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#if defined(CONFIG_NVGPU_HAL_NON_FUSA) && defined(CONFIG_NVGPU_NEXT)
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#include "include/nvgpu/nvgpu_next_err.h"
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#endif
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#endif /* NVGPU_NVGPU_ERR_H */
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