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gpu: nvgpu: gv11b: init therm regs for pwr/clk

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init *eng_delay*, *eng_idle_filt*, *fecs_idle_filter*
and *hubmmu_idle_filter* in therm regs.

Change-Id: I4ab5374084e993cd96ef28ace87b6013b996178d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1570556
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
This commit is contained in:
Seema Khowala
2017-09-28 16:57:16 -07:00
committed by mobile promotions
parent 058485d285
commit f63f96866d
5 changed files with 130 additions and 1 deletions
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1
drivers/gpu/nvgpu/Makefile
View File

@@ -18,6 +18,7 @@ nvgpu-y += \
$(nvgpu-t19x)/gv11b/acr_gv11b.o \
$(nvgpu-t19x)/gv11b/subctx_gv11b.o \
$(nvgpu-t19x)/gv11b/regops_gv11b.o \
$(nvgpu-t19x)/gv11b/therm_gv11b.o \
$(nvgpu-t19x)/gv100/mm_gv100.o \
$(nvgpu-t19x)/gv100/gr_ctx_gv100.o \
$(nvgpu-t19x)/gv100/fb_gv100.o \

3
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -81,6 +81,7 @@
#include "gv11b_gating_reglist.h"
#include "regops_gv11b.h"
#include "subctx_gv11b.h"
#include "therm_gv11b.h"
#include <nvgpu/bus.h>
#include <nvgpu/debug.h>
@@ -553,7 +554,7 @@ static const struct gpu_ops gv11b_ops = {
},
.therm = {
.init_therm_setup_hw = gp10b_init_therm_setup_hw,
.elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
.elcg_init_idle_filters = gv11b_elcg_init_idle_filters,
},
.pmu = {
.pmu_setup_elpg = gp10b_pmu_setup_elpg,

75
drivers/gpu/nvgpu/gv11b/therm_gv11b.c Normal file
View File

@@ -0,0 +1,75 @@
/*
* GV11B Therm
*
* Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#include "gk20a/gk20a.h"
#include <nvgpu/soc.h>
#include <nvgpu/hw/gv11b/hw_therm_gv11b.h>
int gv11b_elcg_init_idle_filters(struct gk20a *g)
{
u32 gate_ctrl, idle_filter;
u32 engine_id;
u32 active_engine_id = 0;
struct fifo_gk20a *f = &g->fifo;
if (nvgpu_platform_is_simulation(g))
return 0;
gk20a_dbg_info("init clock/power gate reg");
for (engine_id = 0; engine_id < f->num_engines; engine_id++) {
active_engine_id = f->active_engines_list[engine_id];
gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(active_engine_id));
gate_ctrl = set_field(gate_ctrl,
therm_gate_ctrl_eng_idle_filt_exp_m(),
therm_gate_ctrl_eng_idle_filt_exp__prod_f());
gate_ctrl = set_field(gate_ctrl,
therm_gate_ctrl_eng_idle_filt_mant_m(),
therm_gate_ctrl_eng_idle_filt_mant__prod_f());
gate_ctrl = set_field(gate_ctrl,
therm_gate_ctrl_eng_delay_before_m(),
therm_gate_ctrl_eng_delay_before__prod_f());
gate_ctrl = set_field(gate_ctrl,
therm_gate_ctrl_eng_delay_after_m(),
therm_gate_ctrl_eng_delay_after__prod_f());
gk20a_writel(g, therm_gate_ctrl_r(active_engine_id), gate_ctrl);
}
idle_filter = gk20a_readl(g, therm_fecs_idle_filter_r());
idle_filter = set_field(idle_filter,
therm_fecs_idle_filter_value_m(),
therm_fecs_idle_filter_value__prod_f());
gk20a_writel(g, therm_fecs_idle_filter_r(), idle_filter);
idle_filter = gk20a_readl(g, therm_hubmmu_idle_filter_r());
idle_filter = set_field(idle_filter,
therm_hubmmu_idle_filter_value_m(),
therm_hubmmu_idle_filter_value__prod_f());
gk20a_writel(g, therm_hubmmu_idle_filter_r(), idle_filter);
return 0;
}

28
drivers/gpu/nvgpu/gv11b/therm_gv11b.h Normal file
View File

@@ -0,0 +1,28 @@
/*
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef THERM_GV11B_H
#define THERM_GV11B_H
struct gk20a;
int gv11b_elcg_init_idle_filters(struct gk20a *g);
#endif /* THERM_GV11B_H */

24
drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_therm_gv11b.h
View File

@@ -240,6 +240,10 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
{
return 0x1f << 8;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_exp__prod_f(void)
{
return 0x200;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
{
return (v & 0x7) << 13;
@@ -248,6 +252,10 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
{
return 0x7 << 13;
}
static inline u32 therm_gate_ctrl_eng_idle_filt_mant__prod_f(void)
{
return 0x2000;
}
static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
{
return (v & 0xf) << 16;
@@ -256,6 +264,10 @@ static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
{
return 0xf << 16;
}
static inline u32 therm_gate_ctrl_eng_delay_before__prod_f(void)
{
return 0x40000;
}
static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
{
return (v & 0xf) << 20;
@@ -264,6 +276,10 @@ static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
{
return 0xf << 20;
}
static inline u32 therm_gate_ctrl_eng_delay_after__prod_f(void)
{
return 0x0;
}
static inline u32 therm_fecs_idle_filter_r(void)
{
return 0x00020288;
@@ -272,6 +288,10 @@ static inline u32 therm_fecs_idle_filter_value_m(void)
{
return 0xffffffff << 0;
}
static inline u32 therm_fecs_idle_filter_value__prod_f(void)
{
return 0x0;
}
static inline u32 therm_hubmmu_idle_filter_r(void)
{
return 0x0002028c;
@@ -280,6 +300,10 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void)
{
return 0xffffffff << 0;
}
static inline u32 therm_hubmmu_idle_filter_value__prod_f(void)
{
return 0x0;
}
static inline u32 therm_clk_slowdown_r(u32 i)
{
return 0x00020160 + i*4;