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gpu: nvgpu: move ltc_tstg_mgmt register setup

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The ltc_ltcs_ltss_tstg_set_mgmt_3 register should only be configured
after ACR init, hence move it down the init order from early_init to
finalize_poweron after acr is loaded.

Bug 3514215

Change-Id: I2462715d25f75b7476ab163cd6c9f73ced5efb6d
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2685547
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Antony Clince Alex
2022-03-23 01:56:27 +00:00
committed by mobile promotions
parent c6f07c14a9
commit f670687441
5 changed files with 16 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
drivers/gpu/nvgpu/common/init/nvgpu_init.c
View File

@@ -900,6 +900,15 @@ int nvgpu_finalize_poweron(struct gk20a *g)
NVGPU_INIT_TABLE_ENTRY(&nvgpu_gr_enable_hw, NO_FLAG), NVGPU_INIT_TABLE_ENTRY(&nvgpu_gr_enable_hw, NO_FLAG),
NVGPU_INIT_TABLE_ENTRY(g->ops.acr.acr_construct_execute, NVGPU_INIT_TABLE_ENTRY(g->ops.acr.acr_construct_execute,
NVGPU_SEC_PRIVSECURITY), NVGPU_SEC_PRIVSECURITY),
/**
* Set ltc_lts_set_mgmt registers only after ACR boot(See
* bug200601972 for details). In order to accomplish this
* ltc_lts_set_mgmt_setup is decoupled from
* nvgpu_init_ltc_support which needs to be executed before ACR
* boot.
*/
NVGPU_INIT_TABLE_ENTRY(g->ops.ltc.ltc_lts_set_mgmt_setup,
NO_FLAG),
/** /**
* Set atomic mode after acr boot(See Bug 3268664 for * Set atomic mode after acr boot(See Bug 3268664 for
* details). For acr to boot, nvgpu_init_fb_support * details). For acr to boot, nvgpu_init_fb_support

4
drivers/gpu/nvgpu/common/ltc/ltc.c
View File

@@ -74,10 +74,6 @@ int nvgpu_init_ltc_support(struct gk20a *g)
} }
} }
if (g->ops.ltc.ltc_lts_set_mgmt_setup != NULL) {
g->ops.ltc.ltc_lts_set_mgmt_setup(g);
}
if (g->ops.ltc.intr.configure != NULL) { if (g->ops.ltc.intr.configure != NULL) {
nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_LTC, nvgpu_cic_mon_intr_stall_unit_config(g, NVGPU_CIC_INTR_UNIT_LTC,
NVGPU_CIC_INTR_ENABLE); NVGPU_CIC_INTR_ENABLE);

4
drivers/gpu/nvgpu/hal/ltc/ltc_ga10b.h
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -38,7 +38,7 @@ void ga10b_ltc_set_zbc_depth_entry(struct gk20a *g, u32 depth_val, u32 index);
#endif #endif
void ga10b_ltc_init_fs_state(struct gk20a *g); void ga10b_ltc_init_fs_state(struct gk20a *g);
void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g); int ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g);
u64 ga10b_determine_L2_size_bytes(struct gk20a *g); u64 ga10b_determine_L2_size_bytes(struct gk20a *g);
int ga10b_lts_ecc_init(struct gk20a *g); int ga10b_lts_ecc_init(struct gk20a *g);

6
drivers/gpu/nvgpu/hal/ltc/ltc_ga10b_fusa.c
View File

@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved. * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
* *
* Permission is hereby granted, free of charge, to any person obtaining a * Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"), * copy of this software and associated documentation files (the "Software"),
@@ -75,7 +75,7 @@ void ga10b_ltc_init_fs_state(struct gk20a *g)
nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r(), reg); nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_1_r(), reg);
} }
void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g) int ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g)
{ {
u32 reg; u32 reg;
@@ -89,6 +89,8 @@ void ga10b_ltc_lts_set_mgmt_setup(struct gk20a *g)
ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_fclr_imm_enabled_f()); ltc_ltcs_ltss_tstg_set_mgmt_3_disallow_clean_fclr_imm_enabled_f());
nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_3_r(), reg); nvgpu_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_3_r(), reg);
} }
return 0;
} }
#ifdef CONFIG_NVGPU_DEBUGGER #ifdef CONFIG_NVGPU_DEBUGGER

2
drivers/gpu/nvgpu/include/nvgpu/gops/ltc.h
View File

@@ -415,7 +415,7 @@ struct gops_ltc {
#if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT) #if defined(CONFIG_NVGPU_NON_FUSA) || defined(CONFIG_NVGPU_KERNEL_MODE_SUBMIT)
void (*set_enabled)(struct gk20a *g, bool enabled); void (*set_enabled)(struct gk20a *g, bool enabled);
#endif #endif
void (*ltc_lts_set_mgmt_setup)(struct gk20a *g); int (*ltc_lts_set_mgmt_setup)(struct gk20a *g);
#ifdef CONFIG_NVGPU_GRAPHICS #ifdef CONFIG_NVGPU_GRAPHICS
void (*set_zbc_color_entry)(struct gk20a *g, void (*set_zbc_color_entry)(struct gk20a *g,
u32 *color_val_l2, u32 index); u32 *color_val_l2, u32 index);