gpu: nvgpu: vgpu: remove gr_ctx handle

gr_ctx can be get from tsgid. RM server wouldn't have to maintain handle
of gr_ctx.

Jira GVSCI-179

Change-Id: Ie143fab1fce21b3f7bf468e12fab31af88d56d40
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1977577
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aparna Das <aparnad@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Richard Zhao
2018-12-20 16:35:25 -08:00
committed by mobile promotions
parent 3b75042842
commit f6874ca733
3 changed files with 1 additions and 8 deletions

View File

@@ -416,10 +416,6 @@ struct nvgpu_gr_ctx {
bool boosted_ctx;
bool golden_img_loaded;
#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION
u64 virt_ctx;
#endif
struct patch_desc patch_ctx;
struct zcull_ctx_desc zcull_ctx;
struct pm_ctx_desc pm_ctx;

View File

@@ -395,7 +395,6 @@ struct tegra_vgpu_ecc_counter_params {
};
struct tegra_vgpu_gr_ctx_params {
u64 gr_ctx_handle;
u64 as_handle;
u64 gr_ctx_va;
u32 class_num;

View File

@@ -335,8 +335,6 @@ int vgpu_gr_alloc_gr_ctx(struct gk20a *g,
__nvgpu_vm_free_va(vm, gr_ctx->mem.gpu_va,
GMMU_PAGE_SIZE_KERNEL);
gr_ctx->mem.aperture = APERTURE_INVALID;
} else {
gr_ctx->virt_ctx = p->gr_ctx_handle;
}
return err;
@@ -429,7 +427,7 @@ void vgpu_gr_free_gr_ctx(struct gk20a *g,
msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE;
msg.handle = vgpu_get_handle(g);
p->gr_ctx_handle = gr_ctx->virt_ctx;
p->tsg_id = gr_ctx->tsgid;
err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
WARN_ON(err || msg.ret);