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gpu: nvgpu: add hal.gr.init hal to load method init bundle

Browse Source 
Add a new hal operation g->ops.gr.init.load_method_init() in hal.gr.init
unit that reads method init netlist bundle and writes those values to
h/w appropriately

Use new hal in gr_gk20a_init_golden_ctx_image() instead of direct
register accesses

Jira NVGPU-2961

Change-Id: If1edd09445e55b5ad9cb1ec7b0f32cab9bfd6f05
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2075227
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Deepak Nibade
2019-03-14 14:49:27 +05:30
committed by mobile promotions
parent d4f7c90020
commit f69050632d
9 changed files with 40 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/gpu/nvgpu/gk20a/gr_gk20a.c
View File

@@ -1041,7 +1041,6 @@ int gr_gk20a_init_golden_ctx_image(struct gk20a *g,
int err = 0;
struct netlist_aiv_list *sw_ctx_load = &g->netlist_vars->sw_ctx_load;
struct netlist_av_list *sw_method_init = &g->netlist_vars->sw_method_init;
u32 last_method_data = 0;
nvgpu_log_fn(g, " ");
@@ -1133,24 +1132,7 @@ restore_fe_go_idle:
}
/* load method init */
if (sw_method_init->count != 0U) {
gk20a_writel(g, gr_pri_mme_shadow_raw_data_r(),
sw_method_init->l[0].value);
gk20a_writel(g, gr_pri_mme_shadow_raw_index_r(),
gr_pri_mme_shadow_raw_index_write_trigger_f() |
sw_method_init->l[0].addr);
last_method_data = sw_method_init->l[0].value;
}
for (i = 1; i < sw_method_init->count; i++) {
if (sw_method_init->l[i].value != last_method_data) {
gk20a_writel(g, gr_pri_mme_shadow_raw_data_r(),
sw_method_init->l[i].value);
last_method_data = sw_method_init->l[i].value;
}
gk20a_writel(g, gr_pri_mme_shadow_raw_index_r(),
gr_pri_mme_shadow_raw_index_write_trigger_f() |
sw_method_init->l[i].addr);
}
g->ops.gr.init.load_method_init(g, sw_method_init);
err = g->ops.gr.init.wait_idle(g);
if (err != 0) {

1
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
View File

@@ -433,6 +433,7 @@ static const struct gpu_ops gm20b_ops = {
.override_context_reset =
gm20b_gr_init_override_context_reset,
.fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout,
.load_method_init = gm20b_gr_init_load_method_init,
},
},
.fb = {

1
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
View File

@@ -505,6 +505,7 @@ static const struct gpu_ops gp10b_ops = {
gm20b_gr_init_override_context_reset,
.preemption_state = gp10b_gr_init_preemption_state,
.fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout,
.load_method_init = gm20b_gr_init_load_method_init,
},
},
.fb = {

1
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -640,6 +640,7 @@ static const struct gpu_ops gv100_ops = {
.override_context_reset =
gm20b_gr_init_override_context_reset,
.fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout,
.load_method_init = gm20b_gr_init_load_method_init,
},
},
.fb = {

1
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -600,6 +600,7 @@ static const struct gpu_ops gv11b_ops = {
gm20b_gr_init_override_context_reset,
.preemption_state = gv11b_gr_init_preemption_state,
.fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout,
.load_method_init = gm20b_gr_init_load_method_init,
},
},
.fb = {

28
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.c
View File

@@ -25,6 +25,7 @@
#include <nvgpu/timers.h>
#include <nvgpu/enabled.h>
#include <nvgpu/engine_status.h>
#include <nvgpu/netlist.h>
#include <nvgpu/gr/gr.h>
#include <nvgpu/gr/config.h>
@@ -303,3 +304,30 @@ void gm20b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable)
gr_fe_go_idle_timeout_count_disabled_f());
}
}
void gm20b_gr_init_load_method_init(struct gk20a *g,
struct netlist_av_list *sw_method_init)
{
u32 i;
u32 last_method_data = 0U;
if (sw_method_init->count != 0U) {
nvgpu_writel(g, gr_pri_mme_shadow_raw_data_r(),
sw_method_init->l[0U].value);
nvgpu_writel(g, gr_pri_mme_shadow_raw_index_r(),
gr_pri_mme_shadow_raw_index_write_trigger_f() |
sw_method_init->l[0U].addr);
last_method_data = sw_method_init->l[0U].value;
}
for (i = 1U; i < sw_method_init->count; i++) {
if (sw_method_init->l[i].value != last_method_data) {
nvgpu_writel(g, gr_pri_mme_shadow_raw_data_r(),
sw_method_init->l[i].value);
last_method_data = sw_method_init->l[i].value;
}
nvgpu_writel(g, gr_pri_mme_shadow_raw_index_r(),
gr_pri_mme_shadow_raw_index_write_trigger_f() |
sw_method_init->l[i].addr);
}
}

3
drivers/gpu/nvgpu/hal/gr/init/gr_init_gm20b.h
View File

@@ -26,6 +26,7 @@
#include <nvgpu/types.h>
struct gk20a;
struct netlist_av_list;
int gm20b_gr_init_fs_state(struct gk20a *g);
void gm20b_gr_init_pd_tpc_per_gpc(struct gk20a *g);
@@ -37,5 +38,7 @@ int gm20b_gr_init_wait_fe_idle(struct gk20a *g);
int gm20b_gr_init_fe_pwr_mode_force_on(struct gk20a *g, bool force_on);
void gm20b_gr_init_override_context_reset(struct gk20a *g);
void gm20b_gr_init_fe_go_idle_timeout(struct gk20a *g, bool enable);
void gm20b_gr_init_load_method_init(struct gk20a *g,
struct netlist_av_list *sw_method_init);
#endif /* NVGPU_GR_INIT_GM20B_H */

3
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -39,6 +39,7 @@ struct gk20a_debug_output;
struct nvgpu_clk_pll_debug_data;
struct nvgpu_nvhost_dev;
struct nvgpu_netlist_vars;
struct netlist_av_list;
struct nvgpu_gr_global_ctx_buffer_desc;
struct nvgpu_gr_fecs_trace;
struct nvgpu_gpu_ctxsw_trace_entry;
@@ -686,6 +687,8 @@ struct gpu_ops {
bool gfxp_wfi_timeout_unit_usec);
void (*fe_go_idle_timeout)(struct gk20a *g,
bool enable);
void (*load_method_init)(struct gk20a *g,
struct netlist_av_list *sw_method_init);
} init;
u32 (*get_ctxsw_checksum_mismatch_mailbox_val)(void);

1
drivers/gpu/nvgpu/tu104/hal_tu104.c
View File

@@ -668,6 +668,7 @@ static const struct gpu_ops tu104_ops = {
gm20b_gr_init_override_context_reset,
.preemption_state = gv11b_gr_init_preemption_state,
.fe_go_idle_timeout = gm20b_gr_init_fe_go_idle_timeout,
.load_method_init = gm20b_gr_init_load_method_init,
},
},
.fb = {