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gpu: nvgpu: Move FB reset to MC unit

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FB reset is done by accessing MC register. Move the code to MC unit.

JIRA NVGPU-954

Change-Id: I1636887af805f016da5490af65e808f9ac015cde
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1823385
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Terje Bergstrom
2018-09-12 14:51:40 -07:00
committed by mobile promotions
parent e3ae03e17a
commit f89ea11041
14 changed files with 15 additions and 34 deletions
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14
drivers/gpu/nvgpu/common/fb/fb_gm20b.c
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@@ -33,25 +33,11 @@
#include <nvgpu/io.h>
#include <nvgpu/timers.h>
#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
#include <nvgpu/hw/gm20b/hw_fb_gm20b.h>
#define VPR_INFO_FETCH_WAIT (5)
#define WPR_INFO_ADDR_ALIGNMENT 0x0000000c
void gm20b_fb_reset(struct gk20a *g)
{
u32 val;
nvgpu_log_info(g, "reset gk20a fb");
val = gk20a_readl(g, mc_elpg_enable_r());
val |= mc_elpg_enable_xbar_enabled_f()
| mc_elpg_enable_pfb_enabled_f()
| mc_elpg_enable_hub_enabled_f();
gk20a_writel(g, mc_elpg_enable_r(), val);
}
void gm20b_fb_init_hw(struct gk20a *g)
{
u64 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8;

1
drivers/gpu/nvgpu/common/fb/fb_gm20b.h
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@@ -31,7 +31,6 @@ struct gk20a;
struct wpr_carveout_info;
struct nvgpu_mem;
void gm20b_fb_reset(struct gk20a *g);
void gm20b_fb_init_hw(struct gk20a *g);
int gm20b_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
void fb_gm20b_init_fs_state(struct gk20a *g);

2
drivers/gpu/nvgpu/common/fb/fb_gp106.c
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@@ -32,7 +32,7 @@
#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */
#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */
void gp106_fb_reset(struct gk20a *g)
void gp106_fb_init_fs_state(struct gk20a *g)
{
u32 val;

2
drivers/gpu/nvgpu/common/fb/fb_gp106.h
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@@ -24,7 +24,7 @@
#define FB_GP106_H
struct gpu_ops;
void gp106_fb_reset(struct gk20a *g);
void gp106_fb_init_fs_state(struct gk20a *g);
size_t gp106_fb_get_vidmem_size(struct gk20a *g);
#endif

7
drivers/gpu/nvgpu/common/fb/fb_gv11b.c
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@@ -73,6 +73,8 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
{
nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb");
gv11b_init_nvlink_soc_credits(g);
nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x",
gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
@@ -143,11 +145,6 @@ void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
}
void gv11b_fb_reset(struct gk20a *g)
{
gv11b_init_nvlink_soc_credits(g);
}
static const char * const invalid_str = "invalid";
static const char *const fault_type_descs_gv11b[] = {

4
drivers/gpu/nvgpu/common/mm/mm.c
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@@ -345,8 +345,8 @@ void nvgpu_init_mm_ce_context(struct gk20a *g)
static int nvgpu_init_mm_reset_enable_hw(struct gk20a *g)
{
if (g->ops.fb.reset) {
g->ops.fb.reset(g);
if (g->ops.mc.fb_reset) {
g->ops.mc.fb_reset(g);
}
if (g->ops.clock_gating.slcg_fb_load_gating_prod) {

2
drivers/gpu/nvgpu/gm20b/hal_gm20b.c
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@@ -330,7 +330,6 @@ static const struct gpu_ops gm20b_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
},
.fb = {
.reset = gm20b_fb_reset,
.init_hw = gm20b_fb_init_hw,
.init_fs_state = fb_gm20b_init_fs_state,
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
@@ -594,6 +593,7 @@ static const struct gpu_ops gm20b_ops = {
.log_pending_intrs = gm20b_mc_log_pending_intrs,
.reset_mask = gm20b_mc_reset_mask,
.is_enabled = gm20b_mc_is_enabled,
.fb_reset = gm20b_mc_fb_reset,
},
.debug = {
.show_dump = gk20a_debug_show_dump,

4
drivers/gpu/nvgpu/gp106/hal_gp106.c
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@@ -406,9 +406,8 @@ static const struct gpu_ops gp106_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
},
.fb = {
.reset = gp106_fb_reset,
.init_hw = gm20b_fb_init_hw,
.init_fs_state = NULL,
.init_fs_state = gp106_fb_init_fs_state,
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
@@ -722,6 +721,7 @@ static const struct gpu_ops gp106_ops = {
.log_pending_intrs = mc_gp10b_log_pending_intrs,
.reset_mask = gm20b_mc_reset_mask,
.is_enabled = gm20b_mc_is_enabled,
.fb_reset = NULL,
},
.debug = {
.show_dump = gk20a_debug_show_dump,

2
drivers/gpu/nvgpu/gp10b/hal_gp10b.c
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@@ -367,7 +367,6 @@ static const struct gpu_ops gp10b_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
},
.fb = {
.reset = gm20b_fb_reset,
.init_hw = gm20b_fb_init_hw,
.init_fs_state = fb_gm20b_init_fs_state,
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
@@ -656,6 +655,7 @@ static const struct gpu_ops gp10b_ops = {
.log_pending_intrs = mc_gp10b_log_pending_intrs,
.reset_mask = gm20b_mc_reset_mask,
.is_enabled = gm20b_mc_is_enabled,
.fb_reset = gm20b_mc_fb_reset,
},
.debug = {
.show_dump = gk20a_debug_show_dump,

5
drivers/gpu/nvgpu/gv100/hal_gv100.c
View File

@@ -31,6 +31,7 @@
#include "common/ptimer/ptimer_gk20a.h"
#include "common/fb/fb_gm20b.h"
#include "common/fb/fb_gp10b.h"
#include "common/fb/fb_gp106.h"
#include "common/fb/fb_gv11b.h"
#include "common/fb/fb_gv100.h"
#include "common/xve/xve_gp106.h"
@@ -467,9 +468,8 @@ static const struct gpu_ops gv100_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
},
.fb = {
.reset = gv100_fb_reset,
.init_hw = gv11b_fb_init_hw,
.init_fs_state = NULL,
.init_fs_state = gp106_fb_init_fs_state,
.set_mmu_page_size = gm20b_fb_set_mmu_page_size,
.set_use_full_comp_tag_line =
gm20b_fb_set_use_full_comp_tag_line,
@@ -819,6 +819,7 @@ static const struct gpu_ops gv100_ops = {
gv100_mc_is_stall_and_eng_intr_pending,
.reset_mask = gv100_mc_reset_mask,
.is_enabled = gm20b_mc_is_enabled,
.fb_reset = NULL,
},
.debug = {
.show_dump = gk20a_debug_show_dump,

2
drivers/gpu/nvgpu/gv11b/hal_gv11b.c
View File

@@ -430,7 +430,6 @@ static const struct gpu_ops gv11b_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
},
.fb = {
.reset = gv11b_fb_reset,
.init_hw = gv11b_fb_init_hw,
.init_fs_state = gv11b_fb_init_fs_state,
.init_cbc = gv11b_fb_init_cbc,
@@ -761,6 +760,7 @@ static const struct gpu_ops gv11b_ops = {
gv11b_mc_is_stall_and_eng_intr_pending,
.reset_mask = gm20b_mc_reset_mask,
.is_enabled = gm20b_mc_is_enabled,
.fb_reset = NULL,
},
.debug = {
.show_dump = gk20a_debug_show_dump,

2
drivers/gpu/nvgpu/include/nvgpu/gk20a.h
View File

@@ -521,7 +521,6 @@ struct gpu_ops {
void (*init_hw)(struct gk20a *g);
void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
void (*init_fs_state)(struct gk20a *g);
void (*reset)(struct gk20a *g);
void (*init_uncompressed_kind_map)(struct gk20a *g);
void (*init_kind_attr)(struct gk20a *g);
void (*set_mmu_page_size)(struct gk20a *g);
@@ -1177,6 +1176,7 @@ struct gpu_ops {
void (*log_pending_intrs)(struct gk20a *g);
void (*fbpa_isr)(struct gk20a *g);
u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit);
void (*fb_reset)(struct gk20a *g);
} mc;
struct {
void (*show_dump)(struct gk20a *g,

1
drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
View File

@@ -236,7 +236,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
},
.fb = {
.reset = NULL,
.init_hw = NULL,
.init_fs_state = NULL,
.set_mmu_page_size = NULL,

1
drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
View File

@@ -276,7 +276,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
.set_debug_mode = gm20b_gr_set_debug_mode,
},
.fb = {
.reset = NULL,
.init_hw = NULL,
.init_fs_state = NULL,
.init_cbc = NULL,