gpu: nvgpu: add GSP falcon support

- Defined FALCON_ID_GSPLITE for GSP falcon.
- Created variable gsp_flcn of struct nvgpu_falcon
  for GSP falcon & registered to falcon module to access
  falcon functions.
- Created HAL file gsp_gv100.c/h for GSP.
- Modified Makefile & Makefile.sources files to include
  gsp_gv100 HAL file.
- Enabled GSP falcon support for GV100 by registering
  to common falcon module.
- Defined function gv100_gsp_reset() & assigned to
  falcon reset as GSP engine reset.
- Updated falcon HAL init code not to return error
  if requested falcon is not supported, instead log
  the info and return non-error.

JIRA NVGPU-1160

Change-Id: Ice032cf443ae87254375265628b3c022f41544cd
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804551
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile

@@ -334,6 +334,7 @@ nvgpu-y += \
 	gv100/hal_gv100.o \
 	gv100/pmu_gv100.o \
 	gv100/perf_gv100.o \
+	gv100/gsp_gv100.o \
 	pstate/pstate.o \
 	clk/clk_vin.o \
 	clk/clk_fll.o \

drivers/gpu/nvgpu/Makefile.sources

@@ -216,4 +216,5 @@ srcs :=	os/posix/nvgpu.c \
 	gv100/nvlink_gv100.c \
 	gv100/hal_gv100.c \
 	gv100/pmu_gv100.c \
-	gv100/perf_gv100.c
+	gv100/perf_gv100.c \
+	gv100/gsp_gv100.c

drivers/gpu/nvgpu/common/falcon/falcon.c

@@ -430,6 +430,10 @@ int nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id)
 		flcn = &g->minion_flcn;
 		flcn->flcn_id = flcn_id;
 		break;
+	case FALCON_ID_GSPLITE:
+		flcn = &g->gsp_flcn;
+		flcn->flcn_id = flcn_id;
+		break;
 	default:
 		nvgpu_err(g, "Invalid/Unsupported falcon ID %x", flcn_id);
 		err = -ENODEV;

drivers/gpu/nvgpu/gk20a/flcn_gk20a.c

@@ -740,8 +740,6 @@ int gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
 		break;
 	default:
 		flcn->is_falcon_supported = false;
-		nvgpu_err(g, "Invalid flcn request");
-		err = -ENODEV;
 		break;
 	}
 

drivers/gpu/nvgpu/gk20a/gk20a.c

@@ -164,6 +164,11 @@ int gk20a_finalize_poweron(struct gk20a *g)
 		nvgpu_err(g, "failed to sw init FALCON_ID_NVDEC");
 		goto done;
 	}
+	err = nvgpu_flcn_sw_init(g, FALCON_ID_GSPLITE);
+	if (err != 0) {
+		nvgpu_err(g, "failed to sw init FALCON_ID_GSPLITE");
+		goto done;
+	}
 
 	if (g->ops.acr.acr_sw_init != NULL &&
 		nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {

drivers/gpu/nvgpu/gp106/flcn_gp106.c

@@ -86,8 +86,6 @@ int gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
 		break;
 	default:
 		flcn->is_falcon_supported = false;
-		nvgpu_err(g, "Invalid flcn request");
-		err = -ENODEV;
 		break;
 	}
 

drivers/gpu/nvgpu/gv100/flcn_gv100.c

@@ -26,29 +26,66 @@
 #include "gk20a/flcn_gk20a.h"
 #include "gp106/flcn_gp106.h"
 #include "gv100/flcn_gv100.h"
+#include "gv100/gsp_gv100.h"
 
 #include <nvgpu/hw/gv100/hw_falcon_gv100.h>
+#include <nvgpu/hw/gv100/hw_pgsp_gv100.h>
+
+static void gv100_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn)
+{
+	struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops =
+			&flcn->flcn_engine_dep_ops;
+
+	switch (flcn->flcn_id) {
+	case FALCON_ID_GSPLITE:
+		flcn_eng_dep_ops->reset_eng = gv100_gsp_reset;
+	break;
+	default:
+		flcn_eng_dep_ops->reset_eng = NULL;
+		break;
+	}
+}
+
+static void gv100_falcon_ops(struct nvgpu_falcon *flcn)
+{
+	gk20a_falcon_ops(flcn);
+	gv100_falcon_engine_dependency_ops(flcn);
+}
 
 int gv100_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
 {
 	struct gk20a *g = flcn->g;
 	int err = 0;
 
-	if (flcn->flcn_id == FALCON_ID_MINION) {
+	switch (flcn->flcn_id) {
+	case FALCON_ID_MINION:
 		flcn->flcn_base = g->nvlink.minion_base;
 		flcn->is_falcon_supported = true;
 		flcn->is_interrupt_enabled = true;
+		break;
+	case FALCON_ID_GSPLITE:
+		flcn->flcn_base = pgsp_falcon_irqsset_r();
+		flcn->is_falcon_supported = true;
+		flcn->is_interrupt_enabled = false;
+		break;
+	default:
+		flcn->is_falcon_supported = false;
+		break;
+	}
 
+	if (flcn->is_falcon_supported) {
 		err = nvgpu_mutex_init(&flcn->copy_lock);
 		if (err != 0) {
 			nvgpu_err(g, "Error in flcn.copy_lock mutex initialization");
-			return err;
+		} else {
+			gv100_falcon_ops(flcn);
 		}
-
-		gk20a_falcon_ops(flcn);
 	} else {
 		/*
-		 * Fall back
+		 * Forward call to previous chips HAL
+		 * to fetch info for requested
+		 * falcon as no changes between
+		 * current & previous chips.
 		 */
 		err = gp106_falcon_hal_sw_init(flcn);
 	}

drivers/gpu/nvgpu/gv100/gsp_gv100.c

@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/falcon.h>
+#include <nvgpu/io.h>
+#include <nvgpu/timers.h>
+
+#include "gk20a/gk20a.h"
+#include "gv100/gsp_gv100.h"
+
+#include <nvgpu/hw/gv100/hw_pgsp_gv100.h>
+
+int gv100_gsp_reset(struct gk20a *g)
+{
+	gk20a_writel(g, pgsp_falcon_engine_r(),
+		pgsp_falcon_engine_reset_true_f());
+	nvgpu_udelay(10);
+	gk20a_writel(g, pgsp_falcon_engine_r(),
+		pgsp_falcon_engine_reset_false_f());
+
+	return 0;
+}

drivers/gpu/nvgpu/gv100/gsp_gv100.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GSP_GV100_H
+#define GSP_GV100_H
+
+int gv100_gsp_reset(struct gk20a *g);
+
+#endif /*GSP_GV100_H */

drivers/gpu/nvgpu/include/nvgpu/falcon.h

@@ -30,6 +30,7 @@
  * Falcon Id Defines
  */
 #define FALCON_ID_PMU       (0U)
+#define FALCON_ID_GSPLITE   (1U)
 #define FALCON_ID_FECS      (2U)
 #define FALCON_ID_GPCCS     (3U)
 #define FALCON_ID_NVDEC     (4U)

drivers/gpu/nvgpu/include/nvgpu/gk20a.h

@@ -1428,6 +1428,7 @@ struct gk20a {
 	struct nvgpu_falcon gpccs_flcn;
 	struct nvgpu_falcon nvdec_flcn;
 	struct nvgpu_falcon minion_flcn;
+	struct nvgpu_falcon gsp_flcn;
 	struct clk_gk20a clk;
 	struct fifo_gk20a fifo;
 	struct nvgpu_nvlink_dev nvlink;