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gpu: nvgpu: doxygen for common.fb hals
Added doxygen documentation for fb hal functions. JIRA NVGPU-4141 Change-Id: I00bf0316c69856596e85314013faddb6f36e765e Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2234440 Reviewed-by: Philip Elcan <pelcan@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Seshendra Gadagottu
committed by
Alex Waterman
Alex Waterman
parent
bac80f7e76
commit
f974bed1bc
@@ -39,9 +39,48 @@ struct gk20a;
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* @see gpu_ops
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*/
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struct gops_fb_intr {
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/**
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* @brief Enable fb hub interrupts.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function enables following fb hub interrupts.
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* MMU_ECC_UNCORRECTED_ERROR_NOTIFY: Uncorrected ECC errors.
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* MMU_NONREPLAYABLE_FAULT_NOTIFY: non-replayable fault happened.
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* MMU_NONREPLAYABLE_FAULT_OVERFLOW : non-replayable fault buffer
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* overflow occurred.
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* MMU_OTHER_FAULT_NOTIFY: All other fault notifications from MMU.
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*/
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void (*enable)(struct gk20a *g);
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/**
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* @brief Disable fb hub interrupts.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function disables fb hub interrupts enabled in enable.
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*/
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void (*disable)(struct gk20a *g);
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/**
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* @brief ISR for fb hub interrupts.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This is the entry point to handle fb hub interrupts. This function
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* handled all the interrupts enabled in enable function.
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*/
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void (*isr)(struct gk20a *g);
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/**
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* @brief Checks any mmu fault interrupt is pending
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function checks and returns information about mmu fault pending.
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*
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* @return true in case of mmu faults pending, false otherwise.
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*/
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bool (*is_mmu_fault_pending)(struct gk20a *g);
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};
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@@ -53,22 +92,198 @@ struct gops_fb_intr {
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* @see gpu_ops
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*/
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struct gops_fb {
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/**
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* @brief Initializes frame buffer h/w configuration.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* Frame Buffer(FB) init h/w function:
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* - configures address that is used for issuing flush reads to
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system memory.
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* - initializes mmu debugger buffer.
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* - enables fb interrupts related to mmu faults.
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*/
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void (*init_hw)(struct gk20a *g);
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/**
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* @brief Intitilizes controls for GMMU state
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function enables platform atomic capability mode to rmw atomic
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* through following configuration:
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* NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE to RMW MODE
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* NV_PFB_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE to L2
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* NV_PFB_HSHUB_NUM_ACTIVE_LTCS_HUB_SYS_ATOMIC_MODE to USE_RMW
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*/
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void (*init_fs_state)(struct gk20a *g);
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void (*set_mmu_page_size)(struct gk20a *g);
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/**
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* @brief Gets master MMU register control
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns register that controls all MMU h/w units.
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*
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* @return u32 register for MMU control.
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*/
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u32 (*mmu_ctrl)(struct gk20a *g);
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/**
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* @brief Gets register control for MMU debug mode
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns register that controls MMU debug mode.
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* In debug mode, MMU translates all faulting engine requests using
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* two dummy pages. One dummy page handles writes, the other dummy
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* page handles reads.
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*
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* @return u32 register for MMU debug mode control.
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*/
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u32 (*mmu_debug_ctrl)(struct gk20a *g);
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/**
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* @brief Gets register address to hold dummy page writes in debug mode.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns register containing the address of the dummy
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* page write in debug mode on a fault.
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*
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* @return u32 register for dummy page write.
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*/
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u32 (*mmu_debug_wr)(struct gk20a *g);
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/**
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* @brief Gets register address to hold dummy page reads in debug mode.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function returns register containing the address of the dummy
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* page read in debug mode on a fault.
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*
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* @return u32 register for dummy page read.
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*/
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u32 (*mmu_debug_rd)(struct gk20a *g);
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/**
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* @brief Dumps VPR information.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function error logs VPR information that the MMU fetches from
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* memory controller. VPR info has following data:
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* - addr_lo displays the lower address of the VPR
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* - addr_hi displays the upper address of the VPR.
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* - cya_low and cya_hi displays CYA bits the control the
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* trust level of each client.
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*/
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void (*dump_vpr_info)(struct gk20a *g);
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/**
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* @brief Dumps WPR information.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function error logs WPR information that the MMU fetches from
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* memory controller. WPR info has following data:
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* - allow_read displays the read access controls
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* - allow_write displays the write access controls
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* - wpr1_addr_lo displays the lower address of the WPR1
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* - wpr1_addr_hi displays the upper address of the WPR1.
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* - wpr2_addr_lo displays the lower address of the WPR2
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* - wpr2_addr_hi displays the upper address of the WPR2.
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*/
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void (*dump_wpr_info)(struct gk20a *g);
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/**
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* @brief Trigger VPR fetch information.
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*
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* @param g [in] Pointer to GPU driver struct.
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*
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* This function triggers VPR fetch and waits until VPR fetch is
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* completed.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ETIMEDOUT if CPU polling timeout during VPR fetch.
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*/
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int (*vpr_info_fetch)(struct gk20a *g);
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/**
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* @brief Read WPR info.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param wpr_base [out] WPR base address.
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* @param wpr_size [out] WPR region size.
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*
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* This function reads WPR info and returns WPR base address and
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* WPR size.
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*/
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void (*read_wpr_info)(struct gk20a *g, u64 *wpr_base, u64 *wpr_size);
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/**
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* @brief Invalidate TLB specific to pdb given.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param pdb [in] Pointer to pdb.
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*
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* This function invalidates all va addressed specified by pdb.
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* It includes following steps:
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* - Wait until pri input fifo space available for tlb invalidation.
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* - Setup pdb address space for invalidation.
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* - Trigger invalidate of all va address and wait for completion.
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*
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* @return 0 in case of success, < 0 in case of failure.
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* @retval -ETIMEDOUT if CPU polling timeout during any tlb invalidate
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* operations.
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*/
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int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb);
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/**
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* @brief Setup mmu fault buffer.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param index [in] Fault buffer index.
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*
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* This function configures mmu fault buffer for h/w and s/w use. When
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* mmu fault occurs h/w will write fault info in the region set-up by
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* s/w for s/w consumption.
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*/
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void (*fault_buf_configure_hw)(struct gk20a *g, u32 index);
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/**
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* @brief Check if mmu fault buffer is enabled or not
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param index [in] Fault buffer index.
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*
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* This function checks and returns whether fault buffer is enabled
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* for specified index.
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*
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* @return true in case of fault buffer enabled, false otherwise.
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*/
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bool (*is_fault_buf_enabled)(struct gk20a *g, u32 index);
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/**
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* @brief Setup mmu fault buffer state.
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*
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* @param g [in] Pointer to GPU driver struct.
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* @param index [in] Fault buffer index.
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* @param state [in] NVGPU_MMU_FAULT_BUF_ENABLED or
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* NVGPU_MMU_FAULT_BUF_DISABLED
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*
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* This function set-up mmu fault buffer state.
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* NVGPU_MMU_FAULT_BUF_ENABLED : set the actual size of fault buffer.
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* NVGPU_MMU_FAULT_BUF_DISABLED : Clears fault buffer size.
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*/
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void (*fault_buf_set_state_hw)(struct gk20a *g, u32 index, u32 state);
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struct gops_fb_intr intr;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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void (*set_mmu_page_size)(struct gk20a *g);
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u32 (*read_mmu_fault_buffer_get)(struct gk20a *g, u32 index);
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u32 (*read_mmu_fault_buffer_put)(struct gk20a *g, u32 index);
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u32 (*read_mmu_fault_buffer_size)(struct gk20a *g, u32 index);
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@@ -86,9 +301,6 @@ struct gops_fb {
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u32 *inst_lo, u32 *inst_hi);
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void (*write_mmu_fault_status)(struct gk20a *g, u32 reg_val);
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struct gops_fb_intr intr;
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/** @cond DOXYGEN_SHOULD_SKIP_THIS */
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struct nvgpu_hw_err_inject_info_desc * (*get_hubmmu_err_desc)
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(struct gk20a *g);
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#ifdef CONFIG_NVGPU_COMPRESSION
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