nvgpu: userspace: update priv_ring testcase

Init below new hals in test_priv_ring_setup:
- priv_ring.isr_handle_0
- priv_ring.isr_handle_1

Jira NVGPU-4669

Change-Id: Ia93a4ffca8335d71a463415d018e0746fc24e07e
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2321415
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Antony Clince Alex
2020-03-31 20:07:31 +05:30
committed by Alex Waterman
parent 5555b6db87
commit fa73b73ba7
2 changed files with 5 additions and 1 deletions

View File

@@ -803,3 +803,5 @@ nvgpu_rc_gr_fault
nvgpu_rc_sched_error_bad_tsg
nvgpu_rc_tsg_and_related_engines
nvgpu_rc_mmu_fault
gp10b_priv_ring_isr_handle_0
gp10b_priv_ring_isr_handle_1

View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -112,6 +112,8 @@ int test_priv_ring_setup(struct unit_module *m, struct gk20a *g, void *args)
/* Init HAL */
g->ops.priv_ring.enable_priv_ring = gm20b_priv_ring_enable;
g->ops.priv_ring.isr = gp10b_priv_ring_isr;
g->ops.priv_ring.isr_handle_0 = gp10b_priv_ring_isr_handle_0;
g->ops.priv_ring.isr_handle_1 = gp10b_priv_ring_isr_handle_1;
g->ops.priv_ring.decode_error_code = gp10b_priv_ring_decode_error_code;
g->ops.priv_ring.set_ppriv_timeout_settings =
gm20b_priv_set_timeout_settings;