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gpu: nvgpu: falcon: fix CERT-C violations

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CERT-C INT-30 requires checking if arithmetic operations will wrap. Use
the safe ops in falcon.c and falcon_gk20a_fusa.c to fix this violation.
Also fix bulk of checkpatch issues.

JIRA NVGPU-3865

Change-Id: I05e53f49dfb19656d325cbb125b36b7ce33b14e4
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2164846
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Sagar Kamble
2019-08-01 10:26:13 +05:30
committed by mobile promotions
parent ade88cfe7c
commit faec0fde02
2 changed files with 133 additions and 147 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/nvgpu/common/falcon/falcon.c
View File

@@ -22,6 +22,7 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/timers.h>
#include <nvgpu/falcon.h>
#include <nvgpu/safe_ops.h>
#include "falcon_sw_gk20a.h"
#ifdef CONFIG_NVGPU_DGPU
@@ -430,7 +431,7 @@ struct nvgpu_falcon *nvgpu_falcon_get_instance(struct gk20a *g, u32 flcn_id)
static int falcon_sw_init(struct gk20a *g, struct nvgpu_falcon *flcn)
{
u32 ver = g->params.gpu_arch + g->params.gpu_impl;
u32 ver = nvgpu_safe_add_u32(g->params.gpu_arch, g->params.gpu_impl);
int err = 0;
switch (ver) {

277
drivers/gpu/nvgpu/hal/falcon/falcon_gk20a_fusa.c
View File

@@ -23,42 +23,46 @@
#include <nvgpu/gk20a.h>
#include <nvgpu/falcon.h>
#include <nvgpu/string.h>
#include <nvgpu/safe_ops.h>
#include "falcon_gk20a.h"
#include <nvgpu/hw/gm20b/hw_falcon_gm20b.h>
static inline u32 gk20a_falcon_readl(struct nvgpu_falcon *flcn, u32 offset)
{
return nvgpu_readl(flcn->g,
nvgpu_safe_add_u32(flcn->flcn_base, offset));
}
static inline void gk20a_falcon_writel(struct nvgpu_falcon *flcn,
u32 offset, u32 val)
{
nvgpu_writel(flcn->g, nvgpu_safe_add_u32(flcn->flcn_base, offset), val);
}
void gk20a_falcon_reset(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
u32 unit_status = 0;
u32 unit_status = 0U;
/* do falcon CPU hard reset */
unit_status = gk20a_readl(g, base_addr +
falcon_falcon_cpuctl_r());
gk20a_writel(g, base_addr + falcon_falcon_cpuctl_r(),
(unit_status | falcon_falcon_cpuctl_hreset_f(1)));
unit_status = gk20a_falcon_readl(flcn, falcon_falcon_cpuctl_r());
gk20a_falcon_writel(flcn, falcon_falcon_cpuctl_r(),
(unit_status | falcon_falcon_cpuctl_hreset_f(1)));
}
bool gk20a_is_falcon_cpu_halted(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
return ((gk20a_readl(g, base_addr + falcon_falcon_cpuctl_r()) &
return ((gk20a_falcon_readl(flcn, falcon_falcon_cpuctl_r()) &
falcon_falcon_cpuctl_halt_intr_m()) != 0U);
}
bool gk20a_is_falcon_idle(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
u32 unit_status = 0;
u32 unit_status = 0U;
bool status = false;
unit_status = gk20a_readl(g,
base_addr + falcon_falcon_idlestate_r());
unit_status = gk20a_falcon_readl(flcn, falcon_falcon_idlestate_r());
if (falcon_falcon_idlestate_falcon_busy_v(unit_status) == 0U &&
falcon_falcon_idlestate_ext_busy_v(unit_status) == 0U) {
@@ -72,13 +76,10 @@ bool gk20a_is_falcon_idle(struct nvgpu_falcon *flcn)
bool gk20a_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
u32 unit_status = 0;
u32 unit_status = 0U;
bool status = false;
unit_status = gk20a_readl(g,
base_addr + falcon_falcon_dmactl_r());
unit_status = gk20a_falcon_readl(flcn, falcon_falcon_dmactl_r());
if ((unit_status &
(falcon_falcon_dmactl_dmem_scrubbing_m() |
@@ -94,16 +95,16 @@ bool gk20a_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn)
u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn,
enum falcon_mem_type mem_type)
{
struct gk20a *g = flcn->g;
u32 mem_size = 0;
u32 hw_cfg_reg = gk20a_readl(g,
flcn->flcn_base + falcon_falcon_hwcfg_r());
u32 mem_size = 0U;
u32 hwcfg_val = 0U;
hwcfg_val = gk20a_falcon_readl(flcn, falcon_falcon_hwcfg_r());
if (mem_type == MEM_DMEM) {
mem_size = falcon_falcon_hwcfg_dmem_size_v(hw_cfg_reg)
mem_size = falcon_falcon_hwcfg_dmem_size_v(hwcfg_val)
<< GK20A_PMU_DMEM_BLKSIZE2;
} else {
mem_size = falcon_falcon_hwcfg_imem_size_v(hw_cfg_reg)
mem_size = falcon_falcon_hwcfg_imem_size_v(hwcfg_val)
<< GK20A_PMU_DMEM_BLKSIZE2;
}
@@ -113,15 +114,15 @@ u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn,
u8 gk20a_falcon_get_ports_count(struct nvgpu_falcon *flcn,
enum falcon_mem_type mem_type)
{
struct gk20a *g = flcn->g;
u8 ports = 0;
u32 hw_cfg_reg1 = gk20a_readl(g,
flcn->flcn_base + falcon_falcon_hwcfg1_r());
u8 ports = 0U;
u32 hwcfg1_val = 0U;
hwcfg1_val = gk20a_falcon_readl(flcn, falcon_falcon_hwcfg1_r());
if (mem_type == MEM_DMEM) {
ports = (u8) falcon_falcon_hwcfg1_dmem_ports_v(hw_cfg_reg1);
ports = (u8) falcon_falcon_hwcfg1_dmem_ports_v(hwcfg1_val);
} else {
ports = (u8) falcon_falcon_hwcfg1_imem_ports_v(hw_cfg_reg1);
ports = (u8) falcon_falcon_hwcfg1_imem_ports_v(hwcfg1_val);
}
return ports;
@@ -130,13 +131,11 @@ u8 gk20a_falcon_get_ports_count(struct nvgpu_falcon *flcn,
int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
u32 dst, u8 *src, u32 size, u8 port)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
u32 i, words, bytes;
u32 data, addr_mask;
u32 i = 0U, words = 0U, bytes = 0U;
u32 data = 0U, addr_mask = 0U;
u32 *src_u32 = (u32 *)src;
nvgpu_log_fn(g, "dest dmem offset - %x, size - %x", dst, size);
nvgpu_log_fn(flcn->g, "dest dmem offset - %x, size - %x", dst, size);
words = size >> 2U;
bytes = size & 0x3U;
@@ -146,25 +145,25 @@ int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
dst &= addr_mask;
nvgpu_writel(g, base_addr + falcon_falcon_dmemc_r(port),
dst | falcon_falcon_dmemc_aincw_f(1));
gk20a_falcon_writel(flcn, falcon_falcon_dmemc_r(port),
dst | falcon_falcon_dmemc_aincw_f(1));
for (i = 0; i < words; i++) {
nvgpu_writel(g, base_addr + falcon_falcon_dmemd_r(port),
src_u32[i]);
gk20a_falcon_writel(flcn, falcon_falcon_dmemd_r(port),
src_u32[i]);
}
if (bytes > 0U) {
data = 0;
nvgpu_memcpy((u8 *)&data, &src[words << 2U], bytes);
nvgpu_writel(g, base_addr + falcon_falcon_dmemd_r(port), data);
gk20a_falcon_writel(flcn, falcon_falcon_dmemd_r(port), data);
}
size = ALIGN(size, 4U);
data = nvgpu_readl(g,
base_addr + falcon_falcon_dmemc_r(port)) & addr_mask;
if (data != ((dst + size) & addr_mask)) {
nvgpu_warn(g, "copy failed. bytes written %d, expected %d",
data = gk20a_falcon_readl(flcn, falcon_falcon_dmemc_r(port)) &
addr_mask;
if (data != (nvgpu_safe_add_u32(dst, size) & addr_mask)) {
nvgpu_warn(flcn->g, "copy failed. bytes written %d, expected %d",
data - dst, size);
}
@@ -174,22 +173,20 @@ int gk20a_falcon_copy_to_dmem(struct nvgpu_falcon *flcn,
int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst,
u8 *src, u32 size, u8 port, bool sec, u32 tag)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
u32 *src_u32 = (u32 *)src;
u32 words = 0;
u32 blk = 0;
u32 i = 0;
u32 words = 0U;
u32 blk = 0U;
u32 i = 0U;
nvgpu_log_info(g, "upload %d bytes to 0x%x", size, dst);
nvgpu_log_info(flcn->g, "upload %d bytes to 0x%x", size, dst);
words = size >> 2U;
blk = dst >> 8;
nvgpu_log_info(g, "upload %d words to 0x%x block %d, tag 0x%x",
nvgpu_log_info(flcn->g, "upload %d words to 0x%x block %d, tag 0x%x",
words, dst, blk, tag);
nvgpu_writel(g, base_addr + falcon_falcon_imemc_r(port),
gk20a_falcon_writel(flcn, falcon_falcon_imemc_r(port),
falcon_falcon_imemc_offs_f(dst >> 2) |
falcon_falcon_imemc_blk_f(blk) |
/* Set Auto-Increment on write */
@@ -199,19 +196,18 @@ int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst,
for (i = 0U; i < words; i++) {
if (i % 64U == 0U) {
/* tag is always 256B aligned */
nvgpu_writel(g,
base_addr + falcon_falcon_imemt_r(port),
tag);
tag++;
gk20a_falcon_writel(flcn, falcon_falcon_imemt_r(port),
tag);
tag = nvgpu_safe_add_u32(tag, 1U);
}
nvgpu_writel(g, base_addr + falcon_falcon_imemd_r(port),
src_u32[i]);
gk20a_falcon_writel(flcn, falcon_falcon_imemd_r(port),
src_u32[i]);
}
/* WARNING : setting remaining bytes in block to 0x0 */
while (i % 64U != 0U) {
nvgpu_writel(g, base_addr + falcon_falcon_imemd_r(port), 0);
gk20a_falcon_writel(flcn, falcon_falcon_imemd_r(port), 0);
i++;
}
@@ -221,18 +217,15 @@ int gk20a_falcon_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst,
int gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn,
u32 boot_vector)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
nvgpu_log_info(flcn->g, "boot vec 0x%x", boot_vector);
nvgpu_log_info(g, "boot vec 0x%x", boot_vector);
gk20a_writel(g, base_addr + falcon_falcon_dmactl_r(),
gk20a_falcon_writel(flcn, falcon_falcon_dmactl_r(),
falcon_falcon_dmactl_require_ctx_f(0));
gk20a_writel(g, base_addr + falcon_falcon_bootvec_r(),
gk20a_falcon_writel(flcn, falcon_falcon_bootvec_r(),
falcon_falcon_bootvec_vec_f(boot_vector));
gk20a_writel(g, base_addr + falcon_falcon_cpuctl_r(),
gk20a_falcon_writel(flcn, falcon_falcon_cpuctl_r(),
falcon_falcon_cpuctl_startcpu_f(1));
return 0;
@@ -241,39 +234,32 @@ int gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn,
u32 gk20a_falcon_mailbox_read(struct nvgpu_falcon *flcn,
u32 mailbox_index)
{
struct gk20a *g = flcn->g;
u32 data = 0;
data = gk20a_readl(g, flcn->flcn_base + (mailbox_index != 0U ?
return gk20a_falcon_readl(flcn, mailbox_index != 0U ?
falcon_falcon_mailbox1_r() :
falcon_falcon_mailbox0_r()));
return data;
falcon_falcon_mailbox0_r());
}
void gk20a_falcon_mailbox_write(struct nvgpu_falcon *flcn,
u32 mailbox_index, u32 data)
{
struct gk20a *g = flcn->g;
gk20a_writel(g,
flcn->flcn_base + (mailbox_index != 0U ?
falcon_falcon_mailbox1_r() :
falcon_falcon_mailbox0_r()),
data);
gk20a_falcon_writel(flcn, mailbox_index != 0U ?
falcon_falcon_mailbox1_r() :
falcon_falcon_mailbox0_r(), data);
}
#ifdef CONFIG_NVGPU_FALCON_DEBUG
static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
u32 i = 0, j = 0;
u32 data[8] = {0};
u32 block_count = 0;
struct gk20a *g = NULL;
u32 i = 0U, j = 0U;
u32 data[8] = {0U};
u32 block_count = 0U;
block_count = falcon_falcon_hwcfg_imem_size_v(gk20a_readl(g,
flcn->flcn_base + falcon_falcon_hwcfg_r()));
g = flcn->g;
block_count = falcon_falcon_hwcfg_imem_size_v(
gk20a_falcon_readl(flcn,
falcon_falcon_hwcfg_r()));
/* block_count must be multiple of 8 */
block_count &= ~0x7U;
@@ -282,13 +268,12 @@ static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn)
for (i = 0U; i < block_count; i += 8U) {
for (j = 0U; j < 8U; j++) {
gk20a_writel(g, flcn->flcn_base +
falcon_falcon_imctl_debug_r(),
gk20a_falcon_writel(flcn, falcon_falcon_imctl_debug_r(),
falcon_falcon_imctl_debug_cmd_f(0x2) |
falcon_falcon_imctl_debug_addr_blk_f(i + j));
data[j] = gk20a_readl(g, base_addr +
falcon_falcon_imstat_r());
data[j] = gk20a_falcon_readl(flcn,
falcon_falcon_imstat_r());
}
nvgpu_err(g, " %#04x: %#010x %#010x %#010x %#010x",
@@ -300,40 +285,42 @@ static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn)
static void gk20a_falcon_dump_pc_trace(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
u32 trace_pc_count = 0;
u32 pc = 0;
u32 i = 0;
struct gk20a *g = NULL;
u32 trace_pc_count = 0U;
u32 pc = 0U;
u32 i = 0U;
if ((gk20a_readl(g,
base_addr + falcon_falcon_sctl_r()) & 0x02U) != 0U) {
g = flcn->g;
if ((gk20a_falcon_readl(flcn, falcon_falcon_sctl_r()) & 0x02U) != 0U) {
nvgpu_err(g, " falcon is in HS mode, PC TRACE dump not supported");
return;
}
trace_pc_count = falcon_falcon_traceidx_maxidx_v(gk20a_readl(g,
base_addr + falcon_falcon_traceidx_r()));
trace_pc_count = falcon_falcon_traceidx_maxidx_v(
gk20a_falcon_readl(flcn,
falcon_falcon_traceidx_r()));
nvgpu_err(g,
"PC TRACE (TOTAL %d ENTRIES. entry 0 is the most recent branch):",
trace_pc_count);
for (i = 0; i < trace_pc_count; i++) {
gk20a_writel(g, base_addr + falcon_falcon_traceidx_r(),
falcon_falcon_traceidx_idx_f(i));
gk20a_falcon_writel(flcn, falcon_falcon_traceidx_r(),
falcon_falcon_traceidx_idx_f(i));
pc = falcon_falcon_tracepc_pc_v(gk20a_readl(g,
base_addr + falcon_falcon_tracepc_r()));
pc = falcon_falcon_tracepc_pc_v(
gk20a_falcon_readl(flcn, falcon_falcon_tracepc_r()));
nvgpu_err(g, "FALCON_TRACEPC(%d) : %#010x", i, pc);
}
}
void gk20a_falcon_dump_stats(struct nvgpu_falcon *flcn)
{
struct gk20a *g = flcn->g;
u32 base_addr = flcn->flcn_base;
struct gk20a *g = NULL;
unsigned int i;
g = flcn->g;
nvgpu_err(g, "<<< FALCON id-%d DEBUG INFORMATION - START >>>",
flcn->flcn_id);
@@ -345,97 +332,95 @@ void gk20a_falcon_dump_stats(struct nvgpu_falcon *flcn)
nvgpu_err(g, "FALCON ICD REGISTERS DUMP");
for (i = 0U; i < 4U; i++) {
gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(),
gk20a_falcon_writel(flcn,
falcon_falcon_icd_cmd_r(),
falcon_falcon_icd_cmd_opc_rreg_f() |
falcon_falcon_icd_cmd_idx_f(FALCON_REG_PC));
nvgpu_err(g, "FALCON_REG_PC : 0x%x",
gk20a_readl(g, base_addr +
falcon_falcon_icd_rdata_r()));
gk20a_falcon_readl(flcn, falcon_falcon_icd_rdata_r()));
gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(),
gk20a_falcon_writel(flcn, falcon_falcon_icd_cmd_r(),
falcon_falcon_icd_cmd_opc_rreg_f() |
falcon_falcon_icd_cmd_idx_f(FALCON_REG_SP));
nvgpu_err(g, "FALCON_REG_SP : 0x%x",
gk20a_readl(g, base_addr +
falcon_falcon_icd_rdata_r()));
gk20a_falcon_readl(flcn, falcon_falcon_icd_rdata_r()));
}
gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(),
gk20a_falcon_writel(flcn, falcon_falcon_icd_cmd_r(),
falcon_falcon_icd_cmd_opc_rreg_f() |
falcon_falcon_icd_cmd_idx_f(FALCON_REG_IMB));
nvgpu_err(g, "FALCON_REG_IMB : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r()));
gk20a_falcon_readl(flcn, falcon_falcon_icd_rdata_r()));
gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(),
gk20a_falcon_writel(flcn, falcon_falcon_icd_cmd_r(),
falcon_falcon_icd_cmd_opc_rreg_f() |
falcon_falcon_icd_cmd_idx_f(FALCON_REG_DMB));
nvgpu_err(g, "FALCON_REG_DMB : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r()));
gk20a_falcon_readl(flcn, falcon_falcon_icd_rdata_r()));
gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(),
gk20a_falcon_writel(flcn, falcon_falcon_icd_cmd_r(),
falcon_falcon_icd_cmd_opc_rreg_f() |
falcon_falcon_icd_cmd_idx_f(FALCON_REG_CSW));
nvgpu_err(g, "FALCON_REG_CSW : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r()));
gk20a_falcon_readl(flcn, falcon_falcon_icd_rdata_r()));
gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(),
gk20a_falcon_writel(flcn, falcon_falcon_icd_cmd_r(),
falcon_falcon_icd_cmd_opc_rreg_f() |
falcon_falcon_icd_cmd_idx_f(FALCON_REG_CTX));
nvgpu_err(g, "FALCON_REG_CTX : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r()));
gk20a_falcon_readl(flcn, falcon_falcon_icd_rdata_r()));
gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(),
gk20a_falcon_writel(flcn, falcon_falcon_icd_cmd_r(),
falcon_falcon_icd_cmd_opc_rreg_f() |
falcon_falcon_icd_cmd_idx_f(FALCON_REG_EXCI));
nvgpu_err(g, "FALCON_REG_EXCI : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_icd_rdata_r()));
gk20a_falcon_readl(flcn, falcon_falcon_icd_rdata_r()));
for (i = 0U; i < 6U; i++) {
gk20a_writel(g, base_addr + falcon_falcon_icd_cmd_r(),
gk20a_falcon_writel(flcn, falcon_falcon_icd_cmd_r(),
falcon_falcon_icd_cmd_opc_rreg_f() |
falcon_falcon_icd_cmd_idx_f(
falcon_falcon_icd_cmd_opc_rstat_f()));
nvgpu_err(g, "FALCON_REG_RSTAT[%d] : 0x%x", i,
gk20a_readl(g, base_addr +
falcon_falcon_icd_rdata_r()));
gk20a_falcon_readl(flcn, falcon_falcon_icd_rdata_r()));
}
nvgpu_err(g, " FALCON REGISTERS DUMP");
nvgpu_err(g, "falcon_falcon_os_r : %d",
gk20a_readl(g, base_addr + falcon_falcon_os_r()));
gk20a_falcon_readl(flcn, falcon_falcon_os_r()));
nvgpu_err(g, "falcon_falcon_cpuctl_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_cpuctl_r()));
gk20a_falcon_readl(flcn, falcon_falcon_cpuctl_r()));
nvgpu_err(g, "falcon_falcon_idlestate_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_idlestate_r()));
gk20a_falcon_readl(flcn, falcon_falcon_idlestate_r()));
nvgpu_err(g, "falcon_falcon_mailbox0_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_mailbox0_r()));
gk20a_falcon_readl(flcn, falcon_falcon_mailbox0_r()));
nvgpu_err(g, "falcon_falcon_mailbox1_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_mailbox1_r()));
gk20a_falcon_readl(flcn, falcon_falcon_mailbox1_r()));
nvgpu_err(g, "falcon_falcon_irqstat_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_irqstat_r()));
gk20a_falcon_readl(flcn, falcon_falcon_irqstat_r()));
nvgpu_err(g, "falcon_falcon_irqmode_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_irqmode_r()));
gk20a_falcon_readl(flcn, falcon_falcon_irqmode_r()));
nvgpu_err(g, "falcon_falcon_irqmask_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_irqmask_r()));
gk20a_falcon_readl(flcn, falcon_falcon_irqmask_r()));
nvgpu_err(g, "falcon_falcon_irqdest_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_irqdest_r()));
gk20a_falcon_readl(flcn, falcon_falcon_irqdest_r()));
nvgpu_err(g, "falcon_falcon_debug1_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_debug1_r()));
gk20a_falcon_readl(flcn, falcon_falcon_debug1_r()));
nvgpu_err(g, "falcon_falcon_debuginfo_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_debuginfo_r()));
gk20a_falcon_readl(flcn, falcon_falcon_debuginfo_r()));
nvgpu_err(g, "falcon_falcon_bootvec_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_bootvec_r()));
gk20a_falcon_readl(flcn, falcon_falcon_bootvec_r()));
nvgpu_err(g, "falcon_falcon_hwcfg_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_hwcfg_r()));
gk20a_falcon_readl(flcn, falcon_falcon_hwcfg_r()));
nvgpu_err(g, "falcon_falcon_engctl_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_engctl_r()));
gk20a_falcon_readl(flcn, falcon_falcon_engctl_r()));
nvgpu_err(g, "falcon_falcon_curctx_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_curctx_r()));
gk20a_falcon_readl(flcn, falcon_falcon_curctx_r()));
nvgpu_err(g, "falcon_falcon_nxtctx_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_nxtctx_r()));
gk20a_falcon_readl(flcn, falcon_falcon_nxtctx_r()));
nvgpu_err(g, "falcon_falcon_exterrstat_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_exterrstat_r()));
gk20a_falcon_readl(flcn, falcon_falcon_exterrstat_r()));
nvgpu_err(g, "falcon_falcon_exterraddr_r : 0x%x",
gk20a_readl(g, base_addr + falcon_falcon_exterraddr_r()));
gk20a_falcon_readl(flcn, falcon_falcon_exterraddr_r()));
}
#endif