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gpu: nvgpu: ACR func/struct version update for FUSA

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-Renamed ACR structs for FUSA, ACR FUSA code has struct names
 ending with _v1 & ACR non-FUSA with _v0, removed _v1 for FUSA
 code to keep struct without any versioning for doxygen.
-Renamed acr_blob_construct_v1.c/h to  acr_blob_construct.c/h

JIRA NVGPU-2516

Change-Id: Id2d5e48e8169ce59371c2b08d04c5a65ba94c685
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2218265
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahantesh Kumbar
2019-10-15 13:46:04 +05:30
committed by Alex Waterman
parent 9e1b540d87
commit fbf219d8ba
14 changed files with 195 additions and 190 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/nvgpu-common.yaml
View File

@@ -216,8 +216,8 @@ acr_fusa:
sources: [ common/acr/acr.c,
common/acr/acr_blob_alloc.c,
common/acr/acr_blob_alloc.h,
common/acr/acr_blob_construct_v1.c,
common/acr/acr_blob_construct_v1.h,
common/acr/acr_blob_construct.c,
common/acr/acr_blob_construct.h,
common/acr/acr_bootstrap.c,
common/acr/acr_bootstrap.h,
common/acr/acr_falcon_bl.h,

2
drivers/gpu/nvgpu/Makefile
View File

@@ -135,7 +135,7 @@ nvgpu-y += \
common/acr/acr_wpr.o \
common/acr/acr_blob_alloc.o \
common/acr/acr_blob_construct_v0.o \
common/acr/acr_blob_construct_v1.o \
common/acr/acr_blob_construct.o \
common/acr/acr_bootstrap.o \
common/acr/acr_sw_gm20b.o \
common/acr/acr_sw_gp10b.o \

2
drivers/gpu/nvgpu/Makefile.sources
View File

@@ -123,7 +123,7 @@ srcs += common/utils/enabled.c \
common/acr/acr.c \
common/acr/acr_wpr.c \
common/acr/acr_blob_alloc.c \
common/acr/acr_blob_construct_v1.c \
common/acr/acr_blob_construct.c \
common/acr/acr_bootstrap.c \
common/acr/acr_sw_gv11b.c \
common/ptimer/ptimer.c \

128
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.c → drivers/gpu/nvgpu/common/acr/acr_blob_construct.c
View File

@@ -28,23 +28,23 @@
#include <nvgpu/gr/gr_falcon.h>
#include <nvgpu/gr/gr_utils.h>
#include "acr_blob_construct_v1.h"
#include "acr_blob_construct.h"
#include "acr_falcon_bl.h"
#include "acr_wpr.h"
#include "acr_priv.h"
#ifdef CONFIG_NVGPU_LS_PMU
int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
int nvgpu_acr_lsf_pmu_ucode_details(struct gk20a *g, void *lsf_ucode_img)
{
struct lsf_ucode_desc_v1 *lsf_desc;
struct lsf_ucode_desc *lsf_desc;
struct nvgpu_firmware *fw_sig;
struct nvgpu_firmware *fw_desc;
struct nvgpu_firmware *fw_image;
struct flcn_ucode_img_v1 *p_img =
(struct flcn_ucode_img_v1 *)lsf_ucode_img;
struct flcn_ucode_img *p_img =
(struct flcn_ucode_img *)lsf_ucode_img;
int err = 0;
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1));
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc));
if (lsf_desc == NULL) {
err = -ENOMEM;
goto exit;
@@ -62,22 +62,22 @@ int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
p_img->desc = (struct ls_falcon_ucode_desc *)(void *)fw_desc->data;
p_img->data = (u32 *)(void *)fw_image->data;
p_img->data_size = p_img->desc->app_start_offset + p_img->desc->app_size;
p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;
p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
exit:
return err;
}
#endif
int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
{
u32 tmp_size;
u32 ver = nvgpu_safe_add_u32(g->params.gpu_arch,
g->params.gpu_impl);
struct lsf_ucode_desc_v1 *lsf_desc;
struct lsf_ucode_desc *lsf_desc;
struct nvgpu_firmware *fecs_sig = NULL;
struct flcn_ucode_img_v1 *p_img =
(struct flcn_ucode_img_v1 *)lsf_ucode_img;
struct flcn_ucode_img *p_img =
(struct flcn_ucode_img *)lsf_ucode_img;
struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g);
struct nvgpu_ctxsw_ucode_segments *fecs =
nvgpu_gr_falcon_get_fecs_ucode_segments(gr_falcon);
@@ -87,10 +87,12 @@ int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
case NVGPU_GPUID_GV11B:
fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG, 0);
break;
#ifdef CONFIG_NVGPU_DGPU
case NVGPU_GPUID_TU104:
fecs_sig = nvgpu_request_firmware(g, TU104_FECS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_SOC);
break;
#endif
default:
nvgpu_err(g, "no support for GPUID %x", ver);
break;
@@ -100,7 +102,7 @@ int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
nvgpu_err(g, "failed to load fecs sig");
return -ENOENT;
}
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1));
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc));
if (lsf_desc == NULL) {
err = -ENOMEM;
goto rel_sig;
@@ -139,7 +141,7 @@ int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
p_img->data = nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon);
p_img->data_size = p_img->desc->image_size;
p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;
p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
nvgpu_acr_dbg(g, "fecs fw loaded\n");
@@ -153,14 +155,14 @@ rel_sig:
return err;
}
int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img)
{
u32 tmp_size;
u32 ver = nvgpu_safe_add_u32(g->params.gpu_arch, g->params.gpu_impl);
struct lsf_ucode_desc_v1 *lsf_desc;
struct lsf_ucode_desc *lsf_desc;
struct nvgpu_firmware *gpccs_sig = NULL;
struct flcn_ucode_img_v1 *p_img =
(struct flcn_ucode_img_v1 *)lsf_ucode_img;
struct flcn_ucode_img *p_img =
(struct flcn_ucode_img *)lsf_ucode_img;
struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g);
struct nvgpu_ctxsw_ucode_segments *gpccs =
nvgpu_gr_falcon_get_gpccs_ucode_segments(gr_falcon);
@@ -174,10 +176,12 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
case NVGPU_GPUID_GV11B:
gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0);
break;
#ifdef CONFIG_NVGPU_DGPU
case NVGPU_GPUID_TU104:
gpccs_sig = nvgpu_request_firmware(g, TU104_GPCCS_UCODE_SIG,
NVGPU_REQUEST_FIRMWARE_NO_SOC);
break;
#endif
default:
nvgpu_err(g, "no support for GPUID %x", ver);
break;
@@ -187,7 +191,7 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
nvgpu_err(g, "failed to load gpccs sig");
return -ENOENT;
}
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1));
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc));
if (lsf_desc == NULL) {
err = -ENOMEM;
goto rel_sig;
@@ -229,7 +233,7 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
(void *)((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon)
+ gpccs->boot.offset);
p_img->data_size = ALIGN(p_img->desc->image_size, 256U);
p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;
p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
nvgpu_acr_dbg(g, "gpccs fw loaded\n");
@@ -244,13 +248,13 @@ rel_sig:
}
#ifdef CONFIG_NVGPU_DGPU
int nvgpu_acr_lsf_sec2_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img)
{
struct nvgpu_firmware *sec2_fw, *sec2_desc, *sec2_sig;
struct ls_falcon_ucode_desc *desc;
struct lsf_ucode_desc_v1 *lsf_desc;
struct flcn_ucode_img_v1 *p_img =
(struct flcn_ucode_img_v1 *)lsf_ucode_img;
struct lsf_ucode_desc *lsf_desc;
struct flcn_ucode_img *p_img =
(struct flcn_ucode_img *)lsf_ucode_img;
u32 *ucode_image;
int err = 0;
@@ -307,7 +311,7 @@ int nvgpu_acr_lsf_sec2_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
goto release_desc;
}
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1));
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc));
if (lsf_desc == NULL) {
err = -ENOMEM;
goto release_sig;
@@ -321,7 +325,7 @@ int nvgpu_acr_lsf_sec2_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img)
p_img->desc = desc;
p_img->data = ucode_image;
p_img->data_size = desc->app_start_offset + desc->app_size;
p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc;
p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
nvgpu_acr_dbg(g, "requesting SEC2 ucode in %s done", g->name);
@@ -338,7 +342,7 @@ release_img_fw:
/* Populate static LSB header information using the provided ucode image */
static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
u32 falcon_id, struct lsfm_managed_ucode_img_v2 *pnode)
u32 falcon_id, struct lsfm_managed_ucode_img *pnode)
{
u32 full_app_size = 0;
u32 data = 0;
@@ -346,7 +350,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
if (pnode->ucode_img.lsf_desc != NULL) {
nvgpu_memcpy((u8 *)&pnode->lsb_header.signature,
(u8 *)pnode->ucode_img.lsf_desc,
sizeof(struct lsf_ucode_desc_v1));
sizeof(struct lsf_ucode_desc));
}
pnode->lsb_header.ucode_size = pnode->ucode_img.data_size;
@@ -397,19 +401,19 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
}
/* Adds a ucode image to the list of managed ucode images managed. */
static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id)
static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr *plsfm,
struct flcn_ucode_img *ucode_image, u32 falcon_id)
{
struct lsfm_managed_ucode_img_v2 *pnode;
struct lsfm_managed_ucode_img *pnode;
pnode = nvgpu_kzalloc(g, sizeof(struct lsfm_managed_ucode_img_v2));
pnode = nvgpu_kzalloc(g, sizeof(struct lsfm_managed_ucode_img));
if (pnode == NULL) {
return -ENOMEM;
}
/* Keep a copy of the ucode image info locally */
nvgpu_memcpy((u8 *)&pnode->ucode_img, (u8 *)ucode_image,
sizeof(struct flcn_ucode_img_v1));
sizeof(struct flcn_ucode_img));
/* Fill in static WPR header info*/
pnode->wpr_header.falcon_id = falcon_id;
@@ -431,9 +435,9 @@ static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm,
/* Discover all managed falcon ucode images */
static int lsfm_discover_ucode_images(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm)
struct ls_flcn_mgr *plsfm)
{
struct flcn_ucode_img_v1 ucode_img;
struct flcn_ucode_img ucode_img;
struct nvgpu_acr *acr = g->acr;
u32 falcon_id;
u32 i;
@@ -483,7 +487,7 @@ exit:
#ifdef CONFIG_NVGPU_DGPU
/* Discover all supported shared data falcon SUB WPRs */
static int lsfm_discover_and_add_sub_wprs(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm)
struct ls_flcn_mgr *plsfm)
{
struct lsfm_sub_wpr *pnode;
u32 size_4K = 0;
@@ -529,9 +533,9 @@ static int lsfm_discover_and_add_sub_wprs(struct gk20a *g,
/* Generate WPR requirements for ACR allocation request */
static int lsf_gen_wpr_requirements(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm)
struct ls_flcn_mgr *plsfm)
{
struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list;
struct lsfm_managed_ucode_img *pnode = plsfm->ucode_img_list;
#ifdef CONFIG_NVGPU_DGPU
struct lsfm_sub_wpr *pnode_sub_wpr = plsfm->psub_wpr_list;
u32 sub_wpr_header;
@@ -544,14 +548,14 @@ static int lsf_gen_wpr_requirements(struct gk20a *g,
* read of this array and cache it internally so it's OK to pack these.
* Also, we add 1 to the falcon count to indicate the end of the array.
*/
wpr_offset = nvgpu_safe_mult_u32(U32(sizeof(struct lsf_wpr_header_v1)),
wpr_offset = nvgpu_safe_mult_u32(U32(sizeof(struct lsf_wpr_header)),
nvgpu_safe_add_u32(U32(plsfm->managed_flcn_cnt), U32(1)));
#ifdef CONFIG_NVGPU_DGPU
if (nvgpu_is_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR)) {
wpr_offset = ALIGN_UP(wpr_offset, LSF_WPR_HEADERS_TOTAL_SIZE_MAX);
/*
* SUB WPR header is appended after LSF_WPR_HEADER in WPR blob.
* SUB WPR header is appended after lsf_wpr_header_v0 in WPR blob.
* The size is allocated as per the managed SUB WPR count.
*/
wpr_offset = ALIGN_UP(wpr_offset, LSF_SUB_WPR_HEADER_ALIGNMENT);
@@ -572,7 +576,7 @@ static int lsf_gen_wpr_requirements(struct gk20a *g,
wpr_offset = ALIGN(wpr_offset, LSF_LSB_HEADER_ALIGNMENT);
pnode->wpr_header.lsb_offset = wpr_offset;
wpr_offset = nvgpu_safe_add_u32(wpr_offset,
(u32)sizeof(struct lsf_lsb_header_v1));
(u32)sizeof(struct lsf_lsb_header));
/*
* Align, save off, and include the original (static)ucode
@@ -653,10 +657,10 @@ static int lsfm_populate_flcn_bl_dmem_desc(struct gk20a *g,
void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid)
{
struct wpr_carveout_info wpr_inf;
struct lsfm_managed_ucode_img_v2 *p_lsfm =
(struct lsfm_managed_ucode_img_v2 *)lsfm;
struct flcn_ucode_img_v1 *p_img = &(p_lsfm->ucode_img);
struct flcn_bl_dmem_desc_v1 *ldr_cfg =
struct lsfm_managed_ucode_img *p_lsfm =
(struct lsfm_managed_ucode_img *)lsfm;
struct flcn_ucode_img *p_img = &(p_lsfm->ucode_img);
struct flcn_bl_dmem_desc *ldr_cfg =
&(p_lsfm->bl_gen_desc);
u64 addr_base;
struct ls_falcon_ucode_desc *desc;
@@ -694,7 +698,7 @@ static int lsfm_populate_flcn_bl_dmem_desc(struct gk20a *g,
/* Populate the LOADER_CONFIG state */
(void) memset((void *) ldr_cfg, 0,
sizeof(struct flcn_bl_dmem_desc_v1));
sizeof(struct flcn_bl_dmem_desc));
ldr_cfg->ctx_dma = g->acr->lsf[falconid].falcon_dma_idx;
flcn64_set_dma(&ldr_cfg->code_dma_base, addr_code);
@@ -711,13 +715,13 @@ static int lsfm_populate_flcn_bl_dmem_desc(struct gk20a *g,
&ldr_cfg->argv);
}
*p_bl_gen_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v1);
*p_bl_gen_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc);
return 0;
}
/* Populate falcon boot loader generic desc.*/
static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
struct lsfm_managed_ucode_img_v2 *pnode)
struct lsfm_managed_ucode_img *pnode)
{
return lsfm_populate_flcn_bl_dmem_desc(g, pnode,
&pnode->bl_gen_desc_size,
@@ -726,7 +730,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
#ifdef CONFIG_NVGPU_DGPU
static void lsfm_init_sub_wpr_contents(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode)
struct ls_flcn_mgr *plsfm, struct nvgpu_mem *ucode)
{
struct lsfm_sub_wpr *psub_wpr_node;
struct lsf_shared_sub_wpr_header last_sub_wpr_header;
@@ -761,17 +765,17 @@ static void lsfm_init_sub_wpr_contents(struct gk20a *g,
#endif
static int lsfm_init_wpr_contents(struct gk20a *g,
struct ls_flcn_mgr_v1 *plsfm, struct nvgpu_mem *ucode)
struct ls_flcn_mgr *plsfm, struct nvgpu_mem *ucode)
{
struct lsfm_managed_ucode_img_v2 *pnode = plsfm->ucode_img_list;
struct lsf_wpr_header_v1 last_wpr_hdr;
struct lsfm_managed_ucode_img *pnode = plsfm->ucode_img_list;
struct lsf_wpr_header last_wpr_hdr;
u32 i;
u64 tmp;
int err = 0;
/* The WPR array is at the base of the WPR */
pnode = plsfm->ucode_img_list;
(void) memset(&last_wpr_hdr, 0, sizeof(struct lsf_wpr_header_v1));
(void) memset(&last_wpr_hdr, 0, sizeof(struct lsf_wpr_header));
i = 0;
#ifdef CONFIG_NVGPU_DGPU
@@ -860,17 +864,17 @@ static int lsfm_init_wpr_contents(struct gk20a *g,
/* Tag the terminator WPR header with an invalid falcon ID. */
last_wpr_hdr.falcon_id = FALCON_ID_INVALID;
tmp = nvgpu_safe_mult_u32(plsfm->managed_flcn_cnt,
(u32)sizeof(struct lsf_wpr_header_v1));
(u32)sizeof(struct lsf_wpr_header));
nvgpu_assert(tmp <= U32_MAX);
nvgpu_mem_wr_n(g, ucode, (u32)tmp, &last_wpr_hdr,
(u32)sizeof(struct lsf_wpr_header_v1));
(u32)sizeof(struct lsf_wpr_header));
return err;
}
/* Free any ucode image structure resources. */
static void lsfm_free_ucode_img_res(struct gk20a *g,
struct flcn_ucode_img_v1 *p_img)
struct flcn_ucode_img *p_img)
{
if (p_img->lsf_desc != NULL) {
nvgpu_kfree(g, p_img->lsf_desc);
@@ -879,7 +883,7 @@ static void lsfm_free_ucode_img_res(struct gk20a *g,
}
static void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g,
struct flcn_ucode_img_v1 *p_img)
struct flcn_ucode_img *p_img)
{
if (p_img->lsf_desc != NULL) {
nvgpu_kfree(g, p_img->lsf_desc);
@@ -891,10 +895,10 @@ static void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g,
}
}
static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm)
static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm)
{
u32 cnt = plsfm->managed_flcn_cnt;
struct lsfm_managed_ucode_img_v2 *mg_ucode_img;
struct lsfm_managed_ucode_img *mg_ucode_img;
while (cnt != 0U) {
mg_ucode_img = plsfm->ucode_img_list;
@@ -911,10 +915,11 @@ static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm)
}
}
int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g)
int nvgpu_acr_prepare_ucode_blob(struct gk20a *g)
{
int err = 0;
struct ls_flcn_mgr_v1 lsfm_l, *plsfm;
struct ls_flcn_mgr lsfm_l, *plsfm;
struct wpr_carveout_info wpr_inf;
struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g);
@@ -923,8 +928,9 @@ int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g)
return err;
}
plsfm = &lsfm_l;
(void) memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v1));
(void) memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr));
err = nvgpu_gr_falcon_init_ctxsw_ucode(g, gr_falcon);
if (err != 0) {
nvgpu_err(g, "gr_falcon_init_ctxsw_ucode failed err=%d", err);

48
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v1.h → drivers/gpu/nvgpu/common/acr/acr_blob_construct.h
View File

@@ -20,8 +20,8 @@
* DEALINGS IN THE SOFTWARE.
*/
#ifndef ACR_BLOB_CONSTRUCT_V1_H
#define ACR_BLOB_CONSTRUCT_V1_H
#ifndef ACR_BLOB_CONSTRUCT_H
#define ACR_BLOB_CONSTRUCT_H
#include <nvgpu/falcon.h>
#include <nvgpu/flcnif_cmn.h>
@@ -46,10 +46,10 @@
* Maximum WPR Header size
*/
#define LSF_WPR_HEADERS_TOTAL_SIZE_MAX \
(ALIGN_UP(((u32)sizeof(struct lsf_wpr_header_v1) * FALCON_ID_END), \
(ALIGN_UP(((u32)sizeof(struct lsf_wpr_header) * FALCON_ID_END), \
LSF_WPR_HEADER_ALIGNMENT))
#define LSF_LSB_HEADER_TOTAL_SIZE_MAX (\
ALIGN_UP(sizeof(struct lsf_lsb_header_v1), LSF_LSB_HEADER_ALIGNMENT))
ALIGN_UP(sizeof(struct lsf_lsb_header), LSF_LSB_HEADER_ALIGNMENT))
#ifdef CONFIG_NVGPU_DGPU
/* Maximum SUB WPR header size */
@@ -105,7 +105,7 @@ enum {
#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5U)
#define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6U)
struct lsf_wpr_header_v1 {
struct lsf_wpr_header {
u32 falcon_id;
u32 lsb_offset;
u32 bootstrap_owner;
@@ -114,7 +114,7 @@ struct lsf_wpr_header_v1 {
u32 status;
};
struct lsf_ucode_desc_v1 {
struct lsf_ucode_desc {
u8 prd_keys[2][16];
u8 dbg_keys[2][16];
u32 b_prd_present;
@@ -127,8 +127,8 @@ struct lsf_ucode_desc_v1 {
u8 kdf[16];
};
struct lsf_lsb_header_v1 {
struct lsf_ucode_desc_v1 signature;
struct lsf_lsb_header {
struct lsf_ucode_desc signature;
u32 ucode_off;
u32 ucode_size;
u32 data_size;
@@ -169,21 +169,21 @@ struct ls_falcon_ucode_desc {
u32 compressed;
};
struct flcn_ucode_img_v1 {
struct flcn_ucode_img {
u32 *data;
struct ls_falcon_ucode_desc *desc;
u32 data_size;
struct lsf_ucode_desc_v1 *lsf_desc;
struct lsf_ucode_desc *lsf_desc;
};
struct lsfm_managed_ucode_img_v2 {
struct lsfm_managed_ucode_img_v2 *next;
struct lsf_wpr_header_v1 wpr_header;
struct lsf_lsb_header_v1 lsb_header;
struct flcn_bl_dmem_desc_v1 bl_gen_desc;
struct lsfm_managed_ucode_img {
struct lsfm_managed_ucode_img *next;
struct lsf_wpr_header wpr_header;
struct lsf_lsb_header lsb_header;
struct flcn_bl_dmem_desc bl_gen_desc;
u32 bl_gen_desc_size;
u32 full_ucode_size;
struct flcn_ucode_img_v1 ucode_img;
struct flcn_ucode_img ucode_img;
};
#ifdef CONFIG_NVGPU_DGPU
@@ -211,24 +211,24 @@ struct lsfm_sub_wpr {
};
#endif
struct ls_flcn_mgr_v1 {
struct ls_flcn_mgr {
u16 managed_flcn_cnt;
u32 wpr_size;
struct lsfm_managed_ucode_img_v2 *ucode_img_list;
struct lsfm_managed_ucode_img *ucode_img_list;
#ifdef CONFIG_NVGPU_DGPU
u16 managed_sub_wpr_count;
struct lsfm_sub_wpr *psub_wpr_list;
#endif
};
int nvgpu_acr_prepare_ucode_blob_v1(struct gk20a *g);
int nvgpu_acr_prepare_ucode_blob(struct gk20a *g);
#ifdef CONFIG_NVGPU_LS_PMU
int nvgpu_acr_lsf_pmu_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_pmu_ucode_details(struct gk20a *g, void *lsf_ucode_img);
#endif
int nvgpu_acr_lsf_fecs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_gpccs_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_fecs_ucode_details(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_gpccs_ucode_details(struct gk20a *g, void *lsf_ucode_img);
#ifdef CONFIG_NVGPU_DGPU
int nvgpu_acr_lsf_sec2_ucode_details_v1(struct gk20a *g, void *lsf_ucode_img);
int nvgpu_acr_lsf_sec2_ucode_details(struct gk20a *g, void *lsf_ucode_img);
#endif
#endif /* ACR_BLOB_CONSTRUCT_V1_H */
#endif /* ACR_BLOB_CONSTRUCT_H */

94
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.c
View File

@@ -38,14 +38,14 @@
#ifdef CONFIG_NVGPU_LS_PMU
int nvgpu_acr_lsf_pmu_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
{
struct lsf_ucode_desc *lsf_desc;
struct lsf_ucode_desc_v0 *lsf_desc;
struct nvgpu_firmware *fw_sig;
struct nvgpu_firmware *fw_desc;
struct nvgpu_firmware *fw_image;
struct flcn_ucode_img *p_img = (struct flcn_ucode_img *)lsf_ucode_img;
struct flcn_ucode_img_v0 *p_img = (struct flcn_ucode_img_v0 *)lsf_ucode_img;
int err = 0;
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc));
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v0));
if (lsf_desc == NULL) {
err = -ENOMEM;
goto exit;
@@ -63,7 +63,7 @@ int nvgpu_acr_lsf_pmu_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
p_img->desc = (struct pmu_ucode_desc *)(void *)fw_desc->data;
p_img->data = (u32 *)(void *)fw_image->data;
p_img->data_size = p_img->desc->image_size;
p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
p_img->lsf_desc = (struct lsf_ucode_desc_v0 *)lsf_desc;
exit:
return err;
@@ -72,9 +72,9 @@ exit:
int nvgpu_acr_lsf_fecs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
{
struct lsf_ucode_desc *lsf_desc;
struct lsf_ucode_desc_v0 *lsf_desc;
struct nvgpu_firmware *fecs_sig;
struct flcn_ucode_img *p_img = (struct flcn_ucode_img *)lsf_ucode_img;
struct flcn_ucode_img_v0 *p_img = (struct flcn_ucode_img_v0 *)lsf_ucode_img;
struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g);
struct nvgpu_ctxsw_ucode_segments *fecs =
nvgpu_gr_falcon_get_fecs_ucode_segments(gr_falcon);
@@ -85,7 +85,7 @@ int nvgpu_acr_lsf_fecs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
nvgpu_err(g, "failed to load fecs sig");
return -ENOENT;
}
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc));
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v0));
if (lsf_desc == NULL) {
err = -ENOMEM;
goto rel_sig;
@@ -122,7 +122,7 @@ int nvgpu_acr_lsf_fecs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
p_img->data = nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon);
p_img->data_size = p_img->desc->image_size;
p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
p_img->lsf_desc = (struct lsf_ucode_desc_v0 *)lsf_desc;
nvgpu_acr_dbg(g, "fecs fw loaded\n");
nvgpu_release_firmware(g, fecs_sig);
return 0;
@@ -135,9 +135,9 @@ rel_sig:
int nvgpu_acr_lsf_gpccs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
{
struct lsf_ucode_desc *lsf_desc;
struct lsf_ucode_desc_v0 *lsf_desc;
struct nvgpu_firmware *gpccs_sig;
struct flcn_ucode_img *p_img = (struct flcn_ucode_img *)lsf_ucode_img;
struct flcn_ucode_img_v0 *p_img = (struct flcn_ucode_img_v0 *)lsf_ucode_img;
struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g);
struct nvgpu_ctxsw_ucode_segments *gpccs =
nvgpu_gr_falcon_get_gpccs_ucode_segments(gr_falcon);
@@ -152,7 +152,7 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
nvgpu_err(g, "failed to load gpccs sig");
return -ENOENT;
}
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc));
lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v0));
if (lsf_desc == NULL) {
err = -ENOMEM;
goto rel_sig;
@@ -191,7 +191,7 @@ int nvgpu_acr_lsf_gpccs_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img)
((u8 *)nvgpu_gr_falcon_get_surface_desc_cpu_va(gr_falcon) +
gpccs->boot.offset);
p_img->data_size = ALIGN(p_img->desc->image_size, 256U);
p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc;
p_img->lsf_desc = (struct lsf_ucode_desc_v0 *)lsf_desc;
nvgpu_acr_dbg(g, "gpccs fw loaded\n");
nvgpu_release_firmware(g, gpccs_sig);
return 0;
@@ -207,7 +207,7 @@ rel_sig:
* Populate static LSB header information using the provided ucode image
*/
static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
u32 falcon_id, struct lsfm_managed_ucode_img *pnode)
u32 falcon_id, struct lsfm_managed_ucode_img_v0 *pnode)
{
u32 full_app_size = 0;
u32 data = 0;
@@ -215,7 +215,7 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
if (pnode->ucode_img.lsf_desc != NULL) {
nvgpu_memcpy((u8 *)&pnode->lsb_header.signature,
(u8 *)pnode->ucode_img.lsf_desc,
sizeof(struct lsf_ucode_desc));
sizeof(struct lsf_ucode_desc_v0));
}
pnode->lsb_header.ucode_size = pnode->ucode_img.data_size;
@@ -261,20 +261,20 @@ static void lsfm_fill_static_lsb_hdr_info(struct gk20a *g,
}
/* Adds a ucode image to the list of managed ucode images managed. */
static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr *plsfm,
struct flcn_ucode_img *ucode_image, u32 falcon_id)
static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v0 *plsfm,
struct flcn_ucode_img_v0 *ucode_image, u32 falcon_id)
{
struct lsfm_managed_ucode_img *pnode;
struct lsfm_managed_ucode_img_v0 *pnode;
pnode = nvgpu_kzalloc(g, sizeof(struct lsfm_managed_ucode_img));
pnode = nvgpu_kzalloc(g, sizeof(struct lsfm_managed_ucode_img_v0));
if (pnode == NULL) {
return -ENOMEM;
}
/* Keep a copy of the ucode image info locally */
nvgpu_memcpy((u8 *)&pnode->ucode_img, (u8 *)ucode_image,
sizeof(struct flcn_ucode_img));
sizeof(struct flcn_ucode_img_v0));
/* Fill in static WPR header info*/
pnode->wpr_header.falcon_id = falcon_id;
@@ -293,9 +293,9 @@ static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr *plsfm,
/* Discover all managed falcon ucode images */
static int lsfm_discover_ucode_images(struct gk20a *g,
struct ls_flcn_mgr *plsfm)
struct ls_flcn_mgr_v0 *plsfm)
{
struct flcn_ucode_img ucode_img;
struct flcn_ucode_img_v0 ucode_img;
struct nvgpu_acr *acr = g->acr;
u32 falcon_id;
u32 i;
@@ -343,9 +343,9 @@ exit:
}
/* Generate WPR requirements for ACR allocation request */
static int lsf_gen_wpr_requirements(struct gk20a *g, struct ls_flcn_mgr *plsfm)
static int lsf_gen_wpr_requirements(struct gk20a *g, struct ls_flcn_mgr_v0 *plsfm)
{
struct lsfm_managed_ucode_img *pnode = plsfm->ucode_img_list;
struct lsfm_managed_ucode_img_v0 *pnode = plsfm->ucode_img_list;
u32 wpr_offset;
/*
@@ -354,7 +354,7 @@ static int lsf_gen_wpr_requirements(struct gk20a *g, struct ls_flcn_mgr *plsfm)
* read of this array and cache it internally so it's OK to pack these.
* Also, we add 1 to the falcon count to indicate the end of the array.
*/
wpr_offset = U32(sizeof(struct lsf_wpr_header)) *
wpr_offset = U32(sizeof(struct lsf_wpr_header_v0)) *
(U32(plsfm->managed_flcn_cnt) + U32(1));
/*
@@ -365,7 +365,7 @@ static int lsf_gen_wpr_requirements(struct gk20a *g, struct ls_flcn_mgr *plsfm)
/* Align, save off, and include an LSB header size */
wpr_offset = ALIGN(wpr_offset, LSF_LSB_HEADER_ALIGNMENT);
pnode->wpr_header.lsb_offset = wpr_offset;
wpr_offset += (u32)sizeof(struct lsf_lsb_header);
wpr_offset += (u32)sizeof(struct lsf_lsb_header_v0);
/*
* Align, save off, and include the original (static)
@@ -425,9 +425,9 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
void *lsfm, u32 *p_bl_gen_desc_size)
{
struct wpr_carveout_info wpr_inf;
struct lsfm_managed_ucode_img *p_lsfm =
(struct lsfm_managed_ucode_img *)lsfm;
struct flcn_ucode_img *p_img = &(p_lsfm->ucode_img);
struct lsfm_managed_ucode_img_v0 *p_lsfm =
(struct lsfm_managed_ucode_img_v0 *)lsfm;
struct flcn_ucode_img_v0 *p_img = &(p_lsfm->ucode_img);
struct loader_config *ldr_cfg = &(p_lsfm->bl_gen_desc.loader_cfg);
u64 addr_base;
struct pmu_ucode_desc *desc;
@@ -497,10 +497,10 @@ static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid)
{
struct wpr_carveout_info wpr_inf;
struct lsfm_managed_ucode_img *p_lsfm =
(struct lsfm_managed_ucode_img *)lsfm;
struct flcn_ucode_img *p_img = &(p_lsfm->ucode_img);
struct flcn_bl_dmem_desc *ldr_cfg =
struct lsfm_managed_ucode_img_v0 *p_lsfm =
(struct lsfm_managed_ucode_img_v0 *)lsfm;
struct flcn_ucode_img_v0 *p_img = &(p_lsfm->ucode_img);
struct flcn_bl_dmem_desc_v0 *ldr_cfg =
&(p_lsfm->bl_gen_desc.bl_dmem_desc);
u64 addr_base;
struct pmu_ucode_desc *desc;
@@ -546,20 +546,20 @@ static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
p_lsfm->wpr_header.falcon_id);
/* Populate the LOADER_CONFIG state */
(void) memset((void *) ldr_cfg, 0, sizeof(struct flcn_bl_dmem_desc));
(void) memset((void *) ldr_cfg, 0, sizeof(struct flcn_bl_dmem_desc_v0));
ldr_cfg->ctx_dma = g->acr->lsf[falconid].falcon_dma_idx;
ldr_cfg->code_dma_base = addr_code;
ldr_cfg->non_sec_code_size = desc->app_resident_code_size;
ldr_cfg->data_dma_base = addr_data;
ldr_cfg->data_size = desc->app_resident_data_size;
ldr_cfg->code_entry_point = desc->app_imem_entry;
*p_bl_gen_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc);
*p_bl_gen_desc_size = (u32)sizeof(struct flcn_bl_dmem_desc_v0);
return 0;
}
/* Populate falcon boot loader generic desc.*/
static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
struct lsfm_managed_ucode_img *pnode)
struct lsfm_managed_ucode_img_v0 *pnode)
{
int err = -ENOENT;
@@ -590,17 +590,17 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g,
return err;
}
static int lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm,
static int lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr_v0 *plsfm,
struct nvgpu_mem *ucode)
{
struct lsfm_managed_ucode_img *pnode = plsfm->ucode_img_list;
struct lsf_wpr_header last_wpr_hdr;
struct lsfm_managed_ucode_img_v0 *pnode = plsfm->ucode_img_list;
struct lsf_wpr_header_v0 last_wpr_hdr;
u32 i;
int err = 0;
/* The WPR array is at the base of the WPR */
pnode = plsfm->ucode_img_list;
(void) memset(&last_wpr_hdr, 0, sizeof(struct lsf_wpr_header));
(void) memset(&last_wpr_hdr, 0, sizeof(struct lsf_wpr_header_v0));
i = 0;
/*
@@ -681,15 +681,15 @@ static int lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm,
last_wpr_hdr.falcon_id = FALCON_ID_INVALID;
nvgpu_mem_wr_n(g, ucode,
(u32)plsfm->managed_flcn_cnt *
(u32)sizeof(struct lsf_wpr_header),
(u32)sizeof(struct lsf_wpr_header_v0),
&last_wpr_hdr,
(u32)sizeof(struct lsf_wpr_header));
(u32)sizeof(struct lsf_wpr_header_v0));
return err;
}
/* Free any ucode image structure resources. */
static void lsfm_free_ucode_img_res(struct gk20a *g,
struct flcn_ucode_img *p_img)
struct flcn_ucode_img_v0 *p_img)
{
if (p_img->lsf_desc != NULL) {
nvgpu_kfree(g, p_img->lsf_desc);
@@ -699,7 +699,7 @@ static void lsfm_free_ucode_img_res(struct gk20a *g,
/* Free any ucode image structure resources. */
static void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g,
struct flcn_ucode_img *p_img)
struct flcn_ucode_img_v0 *p_img)
{
if (p_img->lsf_desc != NULL) {
nvgpu_kfree(g, p_img->lsf_desc);
@@ -711,10 +711,10 @@ static void lsfm_free_nonpmu_ucode_img_res(struct gk20a *g,
}
}
static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm)
static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr_v0 *plsfm)
{
u32 cnt = plsfm->managed_flcn_cnt;
struct lsfm_managed_ucode_img *mg_ucode_img;
struct lsfm_managed_ucode_img_v0 *mg_ucode_img;
while (cnt != 0U) {
mg_ucode_img = plsfm->ucode_img_list;
if (mg_ucode_img->ucode_img.lsf_desc->falcon_id ==
@@ -733,7 +733,7 @@ static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm)
int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g)
{
int err = 0;
struct ls_flcn_mgr lsfm_l, *plsfm;
struct ls_flcn_mgr_v0 lsfm_l, *plsfm;
struct wpr_carveout_info wpr_inf;
struct nvgpu_gr_falcon *gr_falcon = nvgpu_gr_get_falcon_ptr(g);
@@ -742,7 +742,7 @@ int nvgpu_acr_prepare_ucode_blob_v0(struct gk20a *g)
return err;
}
plsfm = &lsfm_l;
(void) memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr));
(void) memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v0));
nvgpu_acr_dbg(g, "fetching GMMU regs\n");
err = g->ops.fb.vpr_info_fetch(g);
if (err != 0) {

28
drivers/gpu/nvgpu/common/acr/acr_blob_construct_v0.h
View File

@@ -70,7 +70,7 @@
* Light Secure WPR Header
* Defines state allowing Light Secure Falcon bootstrapping.
*/
struct lsf_wpr_header {
struct lsf_wpr_header_v0 {
u32 falcon_id;
u32 lsb_offset;
u32 bootstrap_owner;
@@ -82,7 +82,7 @@ struct lsf_wpr_header {
* Light Secure Falcon Ucode Description Defines
* This structure is prelim and may change as the ucode signing flow evolves.
*/
struct lsf_ucode_desc {
struct lsf_ucode_desc_v0 {
u8 prd_keys[2][16];
u8 dbg_keys[2][16];
u32 b_prd_present;
@@ -94,8 +94,8 @@ struct lsf_ucode_desc {
* Light Secure Bootstrap Header
* Defines state allowing Light Secure Falcon bootstrapping.
*/
struct lsf_lsb_header {
struct lsf_ucode_desc signature;
struct lsf_lsb_header_v0 {
struct lsf_ucode_desc_v0 signature;
u32 ucode_off;
u32 ucode_size;
u32 data_size;
@@ -114,16 +114,16 @@ struct lsf_lsb_header {
* Union of all supported structures used by bootloaders.
*/
union flcn_bl_generic_desc {
struct flcn_bl_dmem_desc bl_dmem_desc;
struct flcn_bl_dmem_desc_v0 bl_dmem_desc;
struct loader_config loader_cfg;
};
struct flcn_ucode_img {
struct flcn_ucode_img_v0 {
u32 *data;
struct pmu_ucode_desc *desc; /* only some falcons have descriptor */
u32 data_size;
/* NULL if not a light secure falcon. */
struct lsf_ucode_desc *lsf_desc;
struct lsf_ucode_desc_v0 *lsf_desc;
/* True if there a resources to freed by the client. */
};
@@ -137,14 +137,14 @@ struct flcn_ucode_img {
* full_ucode_size : Surface size required for final ucode image
* ucode_img : Ucode image info
*/
struct lsfm_managed_ucode_img {
struct lsfm_managed_ucode_img *next;
struct lsf_wpr_header wpr_header;
struct lsf_lsb_header lsb_header;
struct lsfm_managed_ucode_img_v0 {
struct lsfm_managed_ucode_img_v0 *next;
struct lsf_wpr_header_v0 wpr_header;
struct lsf_lsb_header_v0 lsb_header;
union flcn_bl_generic_desc bl_gen_desc;
u32 bl_gen_desc_size;
u32 full_ucode_size;
struct flcn_ucode_img ucode_img;
struct flcn_ucode_img_v0 ucode_img;
};
/*
@@ -153,10 +153,10 @@ struct lsfm_managed_ucode_img {
*
* Contains the Light Secure Falcon Manager (LSFM) feature related data.
*/
struct ls_flcn_mgr {
struct ls_flcn_mgr_v0 {
u16 managed_flcn_cnt;
u32 wpr_size;
struct lsfm_managed_ucode_img *ucode_img_list;
struct lsfm_managed_ucode_img_v0 *ucode_img_list;
};
int nvgpu_acr_lsf_pmu_ucode_details_v0(struct gk20a *g, void *lsf_ucode_img);

22
drivers/gpu/nvgpu/common/acr/acr_bootstrap.h
View File

@@ -35,7 +35,7 @@ struct nvgpu_acr;
#define NVGPU_FLCN_ACR_MAX_REGIONS (2U)
#define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200U)
struct flcn_acr_region_prop {
struct flcn_acr_region_prop_v0 {
u32 start_addr;
u32 end_addr;
u32 region_id;
@@ -44,12 +44,12 @@ struct flcn_acr_region_prop {
u32 client_mask;
};
struct flcn_acr_regions {
struct flcn_acr_regions_v0 {
u32 no_regions;
struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
struct flcn_acr_region_prop_v0 region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
};
struct flcn_acr_desc {
struct flcn_acr_desc_v0 {
union {
u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
u32 signatures[4];
@@ -58,7 +58,7 @@ struct flcn_acr_desc {
u32 wpr_region_id;
u32 wpr_offset;
u32 mmu_mem_range;
struct flcn_acr_regions regions;
struct flcn_acr_regions_v0 regions;
u32 nonwpr_ucode_blob_size;
u64 nonwpr_ucode_blob_start;
};
@@ -71,7 +71,7 @@ struct flcn_acr_desc {
* write_mask - WriteMask
* client_mask - Bit map of all clients currently using this region
*/
struct flcn_acr_region_prop_v1 {
struct flcn_acr_region_prop {
u32 start_addr;
u32 end_addr;
u32 region_id;
@@ -85,9 +85,9 @@ struct flcn_acr_region_prop_v1 {
* no_regions - Number of regions used.
* region_props - Region properties
*/
struct flcn_acr_regions_v1 {
struct flcn_acr_regions {
u32 no_regions;
struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS];
};
/*
@@ -105,7 +105,7 @@ struct flcn_acr_regions_v1 {
* nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob
* nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob
*/
struct flcn_acr_desc_v1 {
struct flcn_acr_desc {
union {
u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)];
} ucode_reserved_space;
@@ -114,7 +114,7 @@ struct flcn_acr_desc_v1 {
u32 wpr_region_id;
u32 wpr_offset;
u32 mmu_mem_range;
struct flcn_acr_regions_v1 regions;
struct flcn_acr_regions regions;
u32 nonwpr_ucode_blob_size;
u64 nonwpr_ucode_blob_start;
u32 dummy[4]; /* ACR_BSI_VPR_DESC */
@@ -166,8 +166,8 @@ struct hs_acr {
struct nvgpu_firmware *acr_fw;
union{
struct flcn_acr_desc_v0 *acr_dmem_desc_v0;
struct flcn_acr_desc *acr_dmem_desc;
struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
};
/* Falcon used to execute ACR ucode */

4
drivers/gpu/nvgpu/common/acr/acr_falcon_bl.h
View File

@@ -31,7 +31,7 @@
* to be filled by NVGPU and copied into DMEM at offset provided in the
* hsflcn_bl_desc.bl_desc_dmem_load_off.
*/
struct flcn_bl_dmem_desc {
struct flcn_bl_dmem_desc_v0 {
u32 reserved[4]; /*Should be the first element..*/
u32 signature[4]; /*Should be the first element..*/
u32 ctx_dma;
@@ -47,7 +47,7 @@ struct flcn_bl_dmem_desc {
u32 data_dma_base1;
};
struct flcn_bl_dmem_desc_v1 {
struct flcn_bl_dmem_desc {
u32 reserved[4]; /*Should be the first element..*/
u32 signature[4]; /*Should be the first element..*/
u32 ctx_dma;

2
drivers/gpu/nvgpu/common/acr/acr_priv.h
View File

@@ -27,7 +27,7 @@
#ifdef CONFIG_NVGPU_ACR_LEGACY
#include "acr_blob_construct_v0.h"
#endif
#include "acr_blob_construct_v1.h"
#include "acr_blob_construct.h"
struct gk20a;
struct nvgpu_acr;

8
drivers/gpu/nvgpu/common/acr/acr_sw_gm20b.c
View File

@@ -54,14 +54,14 @@ static void gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct acr_fw_header *acr_fw_hdr = NULL;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct flcn_acr_desc *acr_dmem_desc;
struct flcn_acr_desc_v0 *acr_dmem_desc;
u32 *acr_ucode_header = NULL;
u32 *acr_ucode_data = NULL;
nvgpu_log_fn(g, " ");
if (is_recovery) {
acr_desc->acr_dmem_desc->nonwpr_ucode_blob_size = 0U;
acr_desc->acr_dmem_desc_v0->nonwpr_ucode_blob_size = 0U;
} else {
acr_fw_bin_hdr = (struct bin_hdr *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)
@@ -74,10 +74,10 @@ static void gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
acr_fw_hdr->hdr_offset);
/* Patch WPR info to ucode */
acr_dmem_desc = (struct flcn_acr_desc *)
acr_dmem_desc = (struct flcn_acr_desc_v0 *)
&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
acr_desc->acr_dmem_desc = acr_dmem_desc;
acr_desc->acr_dmem_desc_v0 = acr_dmem_desc;
acr_dmem_desc->nonwpr_ucode_blob_start =
nvgpu_mem_get_addr(g, &g->acr->ucode_blob);

18
drivers/gpu/nvgpu/common/acr/acr_sw_gv11b.c
View File

@@ -31,7 +31,7 @@
#include "acr_wpr.h"
#include "acr_priv.h"
#include "acr_blob_alloc.h"
#include "acr_blob_construct_v1.h"
#include "acr_blob_construct.h"
#include "acr_bootstrap.h"
#include "acr_sw_gv11b.h"
@@ -55,14 +55,14 @@ static void gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct acr_fw_header *acr_fw_hdr = NULL;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct flcn_acr_desc_v1 *acr_dmem_desc;
struct flcn_acr_desc *acr_dmem_desc;
u32 *acr_ucode_header = NULL;
u32 *acr_ucode_data = NULL;
nvgpu_log_fn(g, " ");
if (is_recovery) {
acr_desc->acr_dmem_desc_v1->nonwpr_ucode_blob_size = 0U;
acr_desc->acr_dmem_desc->nonwpr_ucode_blob_size = 0U;
} else {
acr_fw_bin_hdr = (struct bin_hdr *)(void *)acr_fw->data;
acr_fw_hdr = (struct acr_fw_header *)(void *)
@@ -74,10 +74,10 @@ static void gv11b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
acr_fw_hdr->hdr_offset);
/* Patch WPR info to ucode */
acr_dmem_desc = (struct flcn_acr_desc_v1 *)(void *)
acr_dmem_desc = (struct flcn_acr_desc *)(void *)
&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
acr_desc->acr_dmem_desc_v1 = acr_dmem_desc;
acr_desc->acr_dmem_desc = acr_dmem_desc;
acr_dmem_desc->nonwpr_ucode_blob_start =
nvgpu_mem_get_addr(g, &g->acr->ucode_blob);
@@ -104,7 +104,7 @@ static u32 gv11b_acr_lsf_pmu(struct gk20a *g,
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = false;
lsf->is_priv_load = false;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details_v1;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details;
lsf->get_cmd_line_args_offset = nvgpu_pmu_fw_get_cmd_line_args_offset;
return BIT32(lsf->falcon_id);
@@ -124,7 +124,7 @@ static u32 gv11b_acr_lsf_fecs(struct gk20a *g,
*/
lsf->is_lazy_bootstrap = g->support_ls_pmu ? true : false;
lsf->is_priv_load = false;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details_v1;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
@@ -142,7 +142,7 @@ static u32 gv11b_acr_lsf_gpccs(struct gk20a *g,
*/
lsf->is_lazy_bootstrap = g->support_ls_pmu ? true : false;
lsf->is_priv_load = true;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details_v1;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
@@ -188,7 +188,7 @@ void nvgpu_gv11b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
gv11b_acr_default_sw_init(g, &acr->acr);
acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob_v1;
acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob;
acr->get_wpr_info = nvgpu_acr_wpr_info_sys;
acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_sys;
acr->bootstrap_hs_acr = gv11b_bootstrap_hs_acr;

24
drivers/gpu/nvgpu/common/acr/acr_sw_tu104.c
View File

@@ -29,7 +29,7 @@
#include "acr_priv.h"
#include "acr_blob_alloc.h"
#include "acr_bootstrap.h"
#include "acr_blob_construct_v1.h"
#include "acr_blob_construct.h"
#include "acr_sw_gv11b.h"
#include "acr_sw_tu104.h"
@@ -62,7 +62,7 @@ static void tu104_acr_patch_wpr_info_to_ucode(struct gk20a *g,
struct nvgpu_firmware *acr_fw = acr_desc->acr_fw;
struct acr_fw_header *acr_fw_hdr = NULL;
struct bin_hdr *acr_fw_bin_hdr = NULL;
struct flcn_acr_desc_v1 *acr_dmem_desc;
struct flcn_acr_desc *acr_dmem_desc;
struct wpr_carveout_info wpr_inf;
u32 *acr_ucode_header = NULL;
u32 *acr_ucode_data = NULL;
@@ -79,7 +79,7 @@ static void tu104_acr_patch_wpr_info_to_ucode(struct gk20a *g,
acr->get_wpr_info(g, &wpr_inf);
acr_dmem_desc = (struct flcn_acr_desc_v1 *)
acr_dmem_desc = (struct flcn_acr_desc *)
&(((u8 *)acr_ucode_data)[acr_ucode_header[2U]]);
acr_dmem_desc->nonwpr_ucode_blob_start = wpr_inf.nonwpr_base;
@@ -114,7 +114,7 @@ static u32 tu104_acr_lsf_sec2(struct gk20a *g,
lsf->falcon_dma_idx = NV_SEC2_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = false;
lsf->is_priv_load = false;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_sec2_ucode_details_v1;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_sec2_ucode_details;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
@@ -129,7 +129,7 @@ static u32 tu104_acr_lsf_pmu(struct gk20a *g,
lsf->is_lazy_bootstrap = false;
lsf->is_priv_load = false;
#ifdef CONFIG_NVGPU_LS_PMU
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details_v1;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_pmu_ucode_details;
lsf->get_cmd_line_args_offset = nvgpu_pmu_fw_get_cmd_line_args_offset;
#endif
return BIT32(lsf->falcon_id);
@@ -143,7 +143,7 @@ static u32 tu104_acr_lsf_fecs(struct gk20a *g,
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = true;
lsf->is_priv_load = true;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details_v1;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_fecs_ucode_details;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
@@ -157,7 +157,7 @@ static u32 tu104_acr_lsf_gpccs(struct gk20a *g,
lsf->falcon_dma_idx = GK20A_PMU_DMAIDX_UCODE;
lsf->is_lazy_bootstrap = true;
lsf->is_priv_load = true;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details_v1;
lsf->get_lsf_ucode_details = nvgpu_acr_lsf_gpccs_ucode_details;
lsf->get_cmd_line_args_offset = NULL;
return BIT32(lsf->falcon_id);
@@ -182,7 +182,7 @@ static bool tu104_acr_is_fusa_enabled(struct gk20a *g)
}
/* ACR-AHESASC(ACR hub encryption setter and signature checker) init*/
static void tu104_acr_ahesasc_non_fusa_ucode_select(struct gk20a *g,
static void tu104_acr_ahesasc_v0_ucode_select(struct gk20a *g,
struct hs_acr *acr_ahesasc)
{
acr_ahesasc->acr_type = ACR_AHESASC_NON_FUSA;
@@ -213,14 +213,14 @@ static void tu104_acr_ahesasc_sw_init(struct gk20a *g,
if (tu104_acr_is_fusa_enabled(g)) {
tu104_acr_ahesasc_fusa_ucode_select(g, acr_ahesasc);
} else {
tu104_acr_ahesasc_non_fusa_ucode_select(g, acr_ahesasc);
tu104_acr_ahesasc_v0_ucode_select(g, acr_ahesasc);
}
acr_ahesasc->acr_flcn = &g->sec2.flcn;
}
/* ACR-ASB(ACR SEC2 booter) init*/
static void tu104_acr_asb_non_fusa_ucode_select(struct gk20a *g,
static void tu104_acr_asb_v0_ucode_select(struct gk20a *g,
struct hs_acr *acr_asb)
{
acr_asb->acr_type = ACR_ASB_NON_FUSA;
@@ -250,7 +250,7 @@ static void tu104_acr_asb_sw_init(struct gk20a *g,
if (tu104_acr_is_fusa_enabled(g)) {
tu104_acr_asb_fusa_ucode_select(g, acr_asb);
} else {
tu104_acr_asb_non_fusa_ucode_select(g, acr_asb);
tu104_acr_asb_v0_ucode_select(g, acr_asb);
}
acr_asb->acr_flcn = &g->gsp_flcn;
@@ -262,7 +262,7 @@ void nvgpu_tu104_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr)
acr->lsf_enable_mask = tu104_acr_lsf_conifg(g, acr);
acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob_v1;
acr->prepare_ucode_blob = nvgpu_acr_prepare_ucode_blob;
acr->get_wpr_info = nvgpu_acr_wpr_info_vid;
acr->alloc_blob_space = nvgpu_acr_alloc_blob_space_vid;
acr->bootstrap_owner = FALCON_ID_GSPLITE;

1
userspace/units/acr/nvgpu-acr.c
View File

@@ -33,7 +33,6 @@
#include <nvgpu/gr/gr.h>
#include <nvgpu/lock.h>
#include <common/acr/acr_blob_construct_v1.h>
#include <common/acr/acr_wpr.h>
#include <common/acr/acr_priv.h>
#include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>