gpu: nvgpu: add HALs to submit and wait for runlist

Add below two new HALs
gops.fifo.runlist_hw_submit() to submit a new runlist to hardware
gops.fifo.runlist_wait_pending() to wait until runlist write is successful

Set existing API gk20a_fifo_runlist_wait_pending() to
gops.fifo.runlist_wait_pending HAL

Add new API gk20a_fifo_runlist_hw_submit() which submits the runlist to h/w
and set it to gops.fifo.runlist_hw_submit HAL

Jira NVGPUT-20

Change-Id: Ic23f7d947e30883aca0b536de818e79e14733195
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700548
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/gk20a/fifo_gk20a.c

@@ -3217,6 +3217,29 @@ int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
 	return g->ops.fifo.update_runlist(g, tsg->runlist_id, ~0, true, true);
 }
 
+void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+	u32 count, u32 buffer_index)
+{
+	struct fifo_runlist_info_gk20a *runlist = NULL;
+	u64 runlist_iova;
+
+	runlist = &g->fifo.runlist_info[runlist_id];
+	runlist_iova = nvgpu_mem_get_addr(g, &runlist->mem[buffer_index]);
+
+	if (count != 0) {
+		gk20a_writel(g, fifo_runlist_base_r(),
+			fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) |
+			nvgpu_aperture_mask(g, &runlist->mem[buffer_index],
+				fifo_runlist_base_target_sys_mem_ncoh_f(),
+				fifo_runlist_base_target_sys_mem_coh_f(),
+				fifo_runlist_base_target_vid_mem_f()));
+	}
+
+	gk20a_writel(g, fifo_runlist_r(),
+		fifo_runlist_engine_f(runlist_id) |
+		fifo_eng_runlist_length_f(count));
+}
+
 static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
 					    u32 chid, bool add,
 					    bool wait_for_finish)
@@ -3297,21 +3320,10 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
 	} else	/* suspend to remove all channels */
 		count = 0;
 
-	if (count != 0) {
-		gk20a_writel(g, fifo_runlist_base_r(),
-			fifo_runlist_base_ptr_f(u64_lo32(runlist_iova >> 12)) |
-			nvgpu_aperture_mask(g, &runlist->mem[new_buf],
-				fifo_runlist_base_target_sys_mem_ncoh_f(),
-				fifo_runlist_base_target_sys_mem_coh_f(),
-				fifo_runlist_base_target_vid_mem_f()));
-	}
-
-	gk20a_writel(g, fifo_runlist_r(),
-		fifo_runlist_engine_f(runlist_id) |
-		fifo_eng_runlist_length_f(count));
+	g->ops.fifo.runlist_hw_submit(g, runlist_id, count, new_buf);
 
 	if (wait_for_finish) {
-		ret = gk20a_fifo_runlist_wait_pending(g, runlist_id);
+		ret = g->ops.fifo.runlist_wait_pending(g, runlist_id);
 
 		if (ret == -ETIMEDOUT) {
 			nvgpu_err(g,
@@ -3321,7 +3333,7 @@ static int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
 
 			/* engine reset needs the lock. drop it */
 			/* wait until the runlist is active again */
-			ret = gk20a_fifo_runlist_wait_pending(g, runlist_id);
+			ret = g->ops.fifo.runlist_wait_pending(g, runlist_id);
 			/* get the lock back. at this point everything should
 			 * should be fine */
 

drivers/gpu/nvgpu/gk20a/fifo_gk20a.h

@@ -385,6 +385,8 @@ u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f,
 				bool interleave_enabled,
 				bool prev_empty,
 				u32 *entries_left);
+void gk20a_fifo_runlist_hw_submit(struct gk20a *g, u32 runlist_id,
+	u32 count, u32 buffer_index);
 int gk20a_fifo_runlist_wait_pending(struct gk20a *g, u32 runlist_id);
 int gk20a_init_fifo_setup_sw_common(struct gk20a *g);
 int gk20a_init_fifo_setup_sw(struct gk20a *g);

drivers/gpu/nvgpu/gk20a/gk20a.h

@@ -669,6 +669,9 @@ struct gpu_ops {
 				u64 *base_gpuva, u32 *sync_size);
 		u32 (*get_syncpt_incr_per_release)(void);
 #endif
+		void (*runlist_hw_submit)(struct gk20a *g, u32 runlist_id,
+			u32 count, u32 buffer_index);
+		int (*runlist_wait_pending)(struct gk20a *g, u32 runlist_id);
 	} fifo;
 	struct pmu_v {
 		u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);

drivers/gpu/nvgpu/gm20b/hal_gm20b.c

@@ -461,6 +461,8 @@ static const struct gpu_ops gm20b_ops = {
 		.get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
 		.get_sync_ro_map = NULL,
 #endif
+		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
+		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gm20b_get_netlist_name,

drivers/gpu/nvgpu/gp106/hal_gp106.c

@@ -524,6 +524,8 @@ static const struct gpu_ops gp106_ops = {
 #endif
 		.resetup_ramfc = gp10b_fifo_resetup_ramfc,
 		.device_info_fault_id = top_device_info_data_fault_id_enum_v,
+		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
+		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gp106_get_netlist_name,

drivers/gpu/nvgpu/gp10b/hal_gp10b.c

@@ -497,6 +497,8 @@ static const struct gpu_ops gp10b_ops = {
 #endif
 		.resetup_ramfc = gp10b_fifo_resetup_ramfc,
 		.device_info_fault_id = top_device_info_data_fault_id_enum_v,
+		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
+		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gp10b_get_netlist_name,

drivers/gpu/nvgpu/gv100/hal_gv100.c

@@ -585,6 +585,8 @@ static const struct gpu_ops gv100_ops = {
 		.device_info_fault_id = top_device_info_data_fault_id_enum_v,
 		.free_channel_ctx_header = gv11b_free_subctx_header,
 		.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
+		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
+		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gv100_get_netlist_name,

drivers/gpu/nvgpu/gv11b/hal_gv11b.c

@@ -558,6 +558,8 @@ static const struct gpu_ops gv11b_ops = {
 		.free_channel_ctx_header = gv11b_free_subctx_header,
 		.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
 		.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
+		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
+		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gv11b_get_netlist_name,

drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c

@@ -372,6 +372,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
 #endif
 		.resetup_ramfc = NULL,
 		.device_info_fault_id = top_device_info_data_fault_id_enum_v,
+		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
+		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gp10b_get_netlist_name,

drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c

@@ -419,6 +419,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
 		.free_channel_ctx_header = vgpu_gv11b_free_subctx_header,
 		.preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg,
 		.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout,
+		.runlist_hw_submit = gk20a_fifo_runlist_hw_submit,
+		.runlist_wait_pending = gk20a_fifo_runlist_wait_pending,
 	},
 	.gr_ctx = {
 		.get_netlist_name = gr_gv11b_get_netlist_name,