gpu: nvgpu: Add rest of common files to POSIX build

Add common files to POSIX build, and enable most of the common feature
flags nvgpu has enabled in other builds.

As consequence common code now uses more APIs that need to be stubbed
in POSIX build, so add stubs posix-dt.c, posix-nvhost.c, posix-vgpu.c,
and posix-vidmem.c.

JIRA NVGPU-1734

Change-Id: I936c5886229cb4d47cab4f42b013ff77f9e45482
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1993127
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

drivers/gpu/nvgpu/Makefile.sources

@@ -46,6 +46,12 @@ srcs :=	os/posix/nvgpu.c \
 	os/posix/stubs.c \
 	os/posix/posix-fault-injection.c \
 	os/posix/posix-sim.c \
+	os/posix/posix-nvhost.c \
+	os/posix/posix-vgpu.c \
+	os/posix/posix-dt.c \
+	os/posix/posix-vidmem.c \
+	common/sim.c \
+	common/sim_pci.c \
 	common/init/nvgpu_init.c \
 	common/mm/allocators/nvgpu_allocator.c \
 	common/mm/allocators/bitmap_allocator.c \
@@ -62,6 +68,7 @@ srcs :=	os/posix/nvgpu.c \
 	common/mm/comptags.c \
 	common/mm/mm.c \
 	common/mm/dma.c \
+	common/mm/vidmem.c \
 	common/bus/bus_gk20a.c \
 	common/bus/bus_gm20b.c \
 	common/bus/bus_gp10b.c \
@@ -83,6 +90,7 @@ srcs :=	os/posix/nvgpu.c \
 	common/perf/perf_gm20b.c \
 	common/perf/perf_gv11b.c \
 	common/perf/perfbuf.c \
+	common/perf/cyclestats_snapshot.c \
 	common/fuse/fuse_gm20b.c \
 	common/fuse/fuse_gp10b.c \
 	common/fuse/fuse_gp106.c \
@@ -142,6 +150,7 @@ srcs :=	os/posix/nvgpu.c \
 	common/sec2/sec2_ipc.c \
 	common/ptimer/ptimer.c \
 	common/sync/channel_sync.c \
+	common/sync/channel_sync_syncpt.c \
 	common/sync/channel_sync_semaphore.c \
 	common/clock_gating/gm20b_gating_reglist.c \
 	common/clock_gating/gp10b_gating_reglist.c \
@@ -255,4 +264,27 @@ srcs :=	os/posix/nvgpu.c \
 	tu104/hal_tu104.c	\
 	tu104/sec2_tu104.c	\
 	tu104/func_tu104.c	\
-	tu104/regops_tu104.c
+	tu104/regops_tu104.c	\
+	tu104/fecs_trace_tu104.c \
+	vgpu/vgpu.c		\
+	vgpu/fifo_vgpu.c	\
+	vgpu/tsg_vgpu.c		\
+	vgpu/css_vgpu.c		\
+	vgpu/fecs_trace_vgpu.c	\
+	vgpu/mm_vgpu.c		\
+	vgpu/gr_vgpu.c		\
+	vgpu/clk_vgpu.c		\
+	vgpu/dbg_vgpu.c		\
+	vgpu/ltc_vgpu.c		\
+	vgpu/ce2_vgpu.c		\
+	vgpu/gv11b/vgpu_gv11b.c	\
+	vgpu/gv11b/vgpu_hal_gv11b.c \
+	vgpu/gv11b/vgpu_fifo_gv11b.c \
+	vgpu/gv11b/vgpu_tsg_gv11b.c \
+	vgpu/gv11b/vgpu_subctx_gv11b.c \
+	vgpu/gv11b/vgpu_gr_gv11b.c \
+	vgpu/gp10b/vgpu_hal_gp10b.c \
+	vgpu/gp10b/vgpu_fuse_gp10b.c \
+	vgpu/gp10b/vgpu_mm_gp10b.c \
+	vgpu/gp10b/vgpu_gr_gp10b.c \
+	vgpu/gm20b/vgpu_gr_gm20b.c

drivers/gpu/nvgpu/Makefile.tmk

@@ -50,6 +50,17 @@ ifneq ($(NV_BUILD_CONFIGURATION_OS_IS_QNX),1)
 NV_COMPONENT_SYSTEM_SHARED_LIBRARIES += pthread
 endif
 NV_COMPONENT_CFLAGS		+= -D__NVGPU_POSIX__
+
+NV_COMPONENT_CFLAGS            	+= \
+	-DCONFIG_TEGRA_GK20A_NVHOST \
+	-DCONFIG_GK20A_CYCLE_STATS \
+	-DCONFIG_TEGRA_T19X_GRHOST \
+	-DCONFIG_NVGPU_SUPPORT_TURING \
+	-DCONFIG_TEGRA_GK20A_PMU=1 \
+	-DCONFIG_TEGRA_ACR=1 \
+	-DCONFIG_TEGRA_GR_VIRTUALIZATION \
+	-DCONFIG_GK20A_VIDMEM=1 \
+	-DCONFIG_PCI_MSI
 _NV_TOOLCHAIN_CFLAGS            += -rdynamic -g
 
 NV_COMPONENT_SYSTEMIMAGE_DIR    := $(NV_SYSTEMIMAGE_TEST_EXECUTABLE_DIR)/nvgpu_unit

drivers/gpu/nvgpu/os/posix/posix-dt.c

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bug.h>
+#include <nvgpu/dt.h>
+
+int nvgpu_dt_read_u32_index(struct gk20a *g, const char *name,
+				u32 index, u32 *value)
+{
+	BUG();
+	return 0;
+}

drivers/gpu/nvgpu/os/posix/posix-nvhost.c

@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/nvhost.h>
+
+int nvgpu_get_nvhost_dev(struct gk20a *g)
+{
+	BUG();
+	return 0;
+}
+
+void nvgpu_free_nvhost_dev(struct gk20a *g)
+{
+	BUG();
+}
+
+int nvgpu_nvhost_module_busy_ext(
+	struct nvgpu_nvhost_dev *nvhost_dev)
+{
+	BUG();
+	return 0;
+}
+
+void nvgpu_nvhost_module_idle_ext(
+	struct nvgpu_nvhost_dev *nvhost_dev)
+{
+	BUG();
+}
+
+void nvgpu_nvhost_debug_dump_device(
+	struct nvgpu_nvhost_dev *nvhost_dev)
+{
+	BUG();
+}
+
+const char *nvgpu_nvhost_syncpt_get_name(
+	struct nvgpu_nvhost_dev *nvhost_dev, int id)
+{
+	BUG();
+	return NULL;
+}
+
+bool nvgpu_nvhost_syncpt_is_valid_pt_ext(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
+{
+	BUG();
+	return false;
+}
+
+int nvgpu_nvhost_syncpt_is_expired_ext(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 thresh)
+{
+	BUG();
+	return 0;
+}
+
+u32 nvgpu_nvhost_syncpt_incr_max_ext(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 incrs)
+{
+	BUG();
+	return 0U;
+}
+
+int nvgpu_nvhost_intr_register_notifier(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 thresh,
+	void (*callback)(void *, int), void *private_data)
+{
+	BUG();
+	return 0;
+}
+
+void nvgpu_nvhost_syncpt_set_min_eq_max_ext(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
+{
+	BUG();
+}
+
+void nvgpu_nvhost_syncpt_put_ref_ext(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
+{
+	BUG();
+}
+
+u32 nvgpu_nvhost_get_syncpt_host_managed(
+	struct nvgpu_nvhost_dev *nvhost_dev,
+	u32 param, const char *syncpt_name)
+{
+	BUG();
+	return 0U;
+}
+
+u32 nvgpu_nvhost_get_syncpt_client_managed(
+	struct nvgpu_nvhost_dev *nvhost_dev,
+	const char *syncpt_name)
+{
+	BUG();
+	return 0U;
+}
+
+int nvgpu_nvhost_syncpt_wait_timeout_ext(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id,
+	u32 thresh, u32 timeout, u32 *value, struct timespec *ts)
+{
+	BUG();
+	return 0;
+}
+
+int nvgpu_nvhost_syncpt_read_ext_check(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id, u32 *val)
+{
+	BUG();
+	return 0;
+}
+
+u32 nvgpu_nvhost_syncpt_read_maxval(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
+{
+	BUG();
+	return 0U;
+}
+
+void nvgpu_nvhost_syncpt_set_safe_state(
+	struct nvgpu_nvhost_dev *nvhost_dev, u32 id)
+{
+	BUG();
+}
+
+int nvgpu_nvhost_create_symlink(struct gk20a *g)
+{
+	BUG();
+	return 0;
+}
+
+void nvgpu_nvhost_remove_symlink(struct gk20a *g)
+{
+	BUG();
+}
+
+#ifdef CONFIG_SYNC
+u32 nvgpu_nvhost_sync_pt_id(struct sync_pt *pt)
+{
+	BUG();
+	return 0U;
+}
+
+u32 nvgpu_nvhost_sync_pt_thresh(struct sync_pt *pt)
+{
+	BUG();
+	return 0U;
+}
+
+struct sync_fence *nvgpu_nvhost_sync_fdget(int fd)
+{
+	BUG();
+	return NULL;
+}
+
+int nvgpu_nvhost_sync_num_pts(struct sync_fence *fence)
+{
+	BUG();
+	return 0;
+}
+
+struct sync_fence *nvgpu_nvhost_sync_create_fence(
+	struct nvgpu_nvhost_dev *nvhost_dev,
+	u32 id, u32 thresh, const char *name)
+{
+	BUG();
+	return NULL;
+}
+#endif /* CONFIG_SYNC */
+
+#ifdef CONFIG_TEGRA_T19X_GRHOST
+int nvgpu_nvhost_syncpt_unit_interface_get_aperture(
+		struct nvgpu_nvhost_dev *nvhost_dev,
+		u64 *base, size_t *size)
+{
+	BUG();
+	return 0;
+}
+
+u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id)
+{
+	BUG();
+	return 0U;
+}
+
+int nvgpu_nvhost_syncpt_init(struct gk20a *g)
+{
+	return -ENOSYS;
+}
+#endif

drivers/gpu/nvgpu/os/posix/posix-vgpu.c

@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/gk20a.h>
+#include <nvgpu/bug.h>
+#include <nvgpu/vgpu/vgpu.h>
+#include <nvgpu/vgpu/vgpu_ivc.h>
+#include <nvgpu/vgpu/vgpu_ivm.h>
+
+struct vgpu_priv_data *vgpu_get_priv_data(struct gk20a *g)
+{
+	BUG();
+	return NULL;
+}
+
+bool vgpu_is_reduced_bar1(struct gk20a *g)
+{
+	BUG();
+	return false;
+}
+
+int vgpu_ivc_init(struct gk20a *g, u32 elems,
+		const size_t *queue_sizes, u32 queue_start, u32 num_queues)
+{
+	BUG();
+	return 0;
+}
+
+void vgpu_ivc_deinit(u32 queue_start, u32 num_queues)
+{
+	BUG();
+}
+
+void vgpu_ivc_release(void *handle)
+{
+	BUG();
+}
+
+u32 vgpu_ivc_get_server_vmid(void)
+{
+	BUG();
+	return 0U;
+}
+
+int vgpu_ivc_recv(u32 index, void **handle, void **data,
+				size_t *size, u32 *sender)
+{
+	BUG();
+	return 0;
+}
+
+int vgpu_ivc_send(u32 peer, u32 index, void *data, size_t size)
+{
+	BUG();
+	return 0;
+}
+
+int vgpu_ivc_sendrecv(u32 peer, u32 index, void **handle,
+				void **data, size_t *size)
+{
+	BUG();
+	return 0;
+}
+
+u32 vgpu_ivc_get_peer_self(void)
+{
+	BUG();
+	return 0U;
+}
+
+void *vgpu_ivc_oob_get_ptr(u32 peer, u32 index, void **ptr,
+					size_t *size)
+{
+	BUG();
+	return NULL;
+}
+
+void vgpu_ivc_oob_put_ptr(void *handle)
+{
+	BUG();
+}
+
+
+struct tegra_hv_ivm_cookie *vgpu_ivm_mempool_reserve(unsigned int id)
+{
+	BUG();
+	return NULL;
+}
+
+int vgpu_ivm_mempool_unreserve(struct tegra_hv_ivm_cookie *cookie)
+{
+	BUG();
+	return 0;
+}
+
+u64 vgpu_ivm_get_ipa(struct tegra_hv_ivm_cookie *cookie)
+{
+	BUG();
+	return 0ULL;
+}
+
+u64 vgpu_ivm_get_size(struct tegra_hv_ivm_cookie *cookie)
+{
+	BUG();
+	return 0ULL;
+}
+
+void *vgpu_ivm_mempool_map(struct tegra_hv_ivm_cookie *cookie)
+{
+	BUG();
+	return NULL;
+}
+
+void vgpu_ivm_mempool_unmap(struct tegra_hv_ivm_cookie *cookie,
+		void *addr)
+{
+	BUG();
+}
+int vgpu_init_hal_os(struct gk20a *g)
+{
+	BUG();
+	return -ENOSYS;
+}

drivers/gpu/nvgpu/os/posix/posix-vidmem.c

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <nvgpu/bug.h>
+#include <nvgpu/vidmem.h>
+#include <nvgpu/nvgpu_mem.h>
+
+bool nvgpu_addr_is_vidmem_page_alloc(u64 addr)
+{
+	BUG();
+	return false;
+}
+
+void __nvgpu_mem_free_vidmem_alloc(struct gk20a *g, struct nvgpu_mem *vidmem)
+{
+	BUG();
+}

userspace/Makefile.tmk

@@ -93,6 +93,21 @@ endif
 
 NV_COMPONENT_CFLAGS		+= -D__NVGPU_POSIX__
 
+NV_COMPONENT_CFLAGS            	+= \
+	-DCONFIG_TEGRA_19x_GPU \
+	-DCONFIG_TEGRA_GK20A_NVHOST \
+	-DCONFIG_GK20A_CYCLE_STATS \
+	-DCONFIG_TEGRA_T19X_GRHOST \
+	-DCONFIG_NVGPU_SUPPORT_TURING \
+	-DCONFIG_TEGRA_GK20A_PMU=1 \
+	-DCONFIG_TEGRA_ACR=1 \
+	-DCONFIG_TEGRA_GR_VIRTUALIZATION \
+	-DNVCPU_IS_AARCH64=1 \
+	-DCONFIG_TEGRA_IOVMM=0 \
+	-DCONFIG_ARCH_TEGRA_18x_SOC=1 \
+	-DCONFIG_GK20A_VIDMEM=1 \
+	-DCONFIG_PCI_MSI \
+	-DCONFIG_SUPPORT_PMU_PSTATE
 NV_COMPONENT_SYSTEMIMAGE_DIR    := $(NV_SYSTEMIMAGE_TEST_EXECUTABLE_DIR)/nvgpu_unit/
 systemimage:: $(NV_COMPONENT_SYSTEMIMAGE_DIR)
 $(NV_COMPONENT_SYSTEMIMAGE_DIR) : $(NV_SYSTEMIMAGE_TEST_EXECUTABLE_DIR)

userspace/units/Makefile.units.common.tmk

@@ -36,6 +36,21 @@ endif
 
 NV_COMPONENT_CFLAGS		+= -D__NVGPU_POSIX__
 
+NV_COMPONENT_CFLAGS            	+= \
+	-DCONFIG_TEGRA_19x_GPU \
+	-DCONFIG_TEGRA_GK20A_NVHOST \
+	-DCONFIG_GK20A_CYCLE_STATS \
+	-DCONFIG_TEGRA_T19X_GRHOST \
+	-DCONFIG_NVGPU_SUPPORT_TURING \
+	-DCONFIG_TEGRA_GK20A_PMU=1 \
+	-DCONFIG_TEGRA_ACR=1 \
+	-DCONFIG_TEGRA_GR_VIRTUALIZATION \
+	-DNVCPU_IS_AARCH64=1 \
+	-DCONFIG_TEGRA_IOVMM=0 \
+	-DCONFIG_ARCH_TEGRA_18x_SOC=1 \
+	-DCONFIG_GK20A_VIDMEM=1 \
+	-DCONFIG_PCI_MSI \
+	-DCONFIG_SUPPORT_PMU_PSTATE
 NV_COMPONENT_NEEDED_INTERFACE_DIRS += \
                                 $(NV_SOURCE)/kernel/nvgpu/drivers/gpu/nvgpu \
                                 $(NV_SOURCE)/kernel/nvgpu/userspace