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gpu_ nvgpu: fix misra errors in gr units

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Fix MISRA 8.6 violation in gr config and interrupt units.
Rule 8.6 requires each identifier with external linkage to have
exactly one external definitions.

Move unused function definitions under CONFIG_NVGPU_HAL_NON_FUSA
checking.

Jira NVGPU-3854

Change-Id: I0661ea00ef9df700b0b928c8bf77e9a0fa4be29b
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2171386
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Vinod G
2019-08-08 14:43:17 -07:00
committed by mobile promotions
parent 0e873d6348
commit fece8bb1b7
4 changed files with 24 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
drivers/gpu/nvgpu/hal/gr/config/gr_config_gm20b.h
View File

@@ -28,20 +28,21 @@
struct gk20a;
struct nvgpu_gr_config;
int gm20b_gr_config_init_sm_id_table(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
u32 gm20b_gr_config_get_gpc_tpc_mask(struct gk20a *g,
struct nvgpu_gr_config *config, u32 gpc_index);
u32 gm20b_gr_config_get_tpc_count_in_gpc(struct gk20a *g,
struct nvgpu_gr_config *config, u32 gpc_index);
#ifdef CONFIG_NVGPU_GRAPHICS
u32 gm20b_gr_config_get_zcull_count_in_gpc(struct gk20a *g,
struct nvgpu_gr_config *config, u32 gpc_index);
#endif
u32 gm20b_gr_config_get_pes_tpc_mask(struct gk20a *g,
struct nvgpu_gr_config *config, u32 gpc_index, u32 pes_index);
u32 gm20b_gr_config_get_pd_dist_skip_table_size(void);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
u32 gm20b_gr_config_get_gpc_mask(struct gk20a *g,
struct nvgpu_gr_config *config);
int gm20b_gr_config_init_sm_id_table(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
#ifdef CONFIG_NVGPU_GRAPHICS
u32 gm20b_gr_config_get_zcull_count_in_gpc(struct gk20a *g,
struct nvgpu_gr_config *config, u32 gpc_index);
#endif /* CONFIG_NVGPU_GRAPHICS */
#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
#endif /* NVGPU_GR_CONFIG_GM20B_H */

6
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.h
View File

@@ -36,14 +36,16 @@ void gm20b_ctxsw_prog_set_patch_addr(struct gk20a *g,
struct nvgpu_mem *ctx_mem, u64 addr);
void gm20b_ctxsw_prog_init_ctxsw_hdr_data(struct gk20a *g,
struct nvgpu_mem *ctx_mem);
void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g,
struct nvgpu_mem *ctx_mem);
void gm20b_ctxsw_prog_set_priv_access_map_config_mode(struct gk20a *g,
struct nvgpu_mem *ctx_mem, bool allow_all);
void gm20b_ctxsw_prog_set_priv_access_map_addr(struct gk20a *g,
struct nvgpu_mem *ctx_mem, u64 addr);
void gm20b_ctxsw_prog_disable_verif_features(struct gk20a *g,
struct nvgpu_mem *ctx_mem);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gm20b_ctxsw_prog_set_compute_preemption_mode_cta(struct gk20a *g,
struct nvgpu_mem *ctx_mem);
#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
#ifdef CONFIG_NVGPU_GRAPHICS
void gm20b_ctxsw_prog_set_zcull_ptr(struct gk20a *g, struct nvgpu_mem *ctx_mem,
u64 addr);

19
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gm20b.h
View File

@@ -40,9 +40,6 @@ struct nvgpu_gr_intr_info;
#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE U32(0)
int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data);
void gm20b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data);
void gm20b_gr_intr_handle_class_error(struct gk20a *g, u32 chid,
struct nvgpu_gr_isr_data *isr_data);
void gm20b_gr_intr_clear_pending_interrupts(struct gk20a *g, u32 gr_intr);
@@ -56,18 +53,21 @@ void gm20b_gr_intr_get_trapped_method_info(struct gk20a *g,
struct nvgpu_gr_isr_data *isr_data);
u32 gm20b_gr_intr_get_tpc_exception(struct gk20a *g, u32 offset,
struct nvgpu_gr_tpc_exception *pending_tpc);
void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable);
u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g);
void gm20ab_gr_intr_tpc_exception_sm_disable(struct gk20a *g, u32 offset);
void gm20ab_gr_intr_tpc_exception_sm_enable(struct gk20a *g);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
int gm20b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data);
void gm20b_gr_intr_set_shader_exceptions(struct gk20a *g, u32 data);
void gm20b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc);
void gm20b_gr_intr_enable_hww_exceptions(struct gk20a *g);
void gm20b_gr_intr_enable_interrupts(struct gk20a *g, bool enable);
void gm20b_gr_intr_enable_exceptions(struct gk20a *g,
struct nvgpu_gr_config *gr_config,
bool enable);
void gm20b_gr_intr_enable_gpc_exceptions(struct gk20a *g,
struct nvgpu_gr_config *gr_config);
u32 gm20b_gr_intr_nonstall_isr(struct gk20a *g);
void gm20ab_gr_intr_tpc_exception_sm_disable(struct gk20a *g, u32 offset);
void gm20ab_gr_intr_tpc_exception_sm_enable(struct gk20a *g);
void gm20b_gr_intr_set_hww_esr_report_mask(struct gk20a *g);
void gm20b_gr_intr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc,
u32 *esr_sm_sel);
@@ -80,8 +80,9 @@ u32 gm20b_gr_intr_get_sm_hww_global_esr(struct gk20a *g, u32 gpc, u32 tpc,
u32 sm);
u32 gm20b_gr_intr_get_sm_hww_warp_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm);
u32 gm20b_gr_intr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
#ifdef CONFIG_NVGPU_DEBUGGER
u64 gm20b_gr_intr_tpc_enabled_exceptions(struct gk20a *g);
#endif
#endif /* CONFIG_NVGPU_DEBUGGER */
#endif /* NVGPU_GR_INTR_GM20B_H */

2
drivers/gpu/nvgpu/hal/gr/intr/gr_intr_gp10b.h
View File

@@ -45,6 +45,7 @@ int gp10b_gr_intr_handle_fecs_error(struct gk20a *g,
struct nvgpu_gr_isr_data *isr_data);
void gp10b_gr_intr_set_coalesce_buffer_size(struct gk20a *g, u32 data);
void gp10b_gr_intr_set_go_idle_timeout(struct gk20a *g, u32 data);
#ifdef CONFIG_NVGPU_HAL_NON_FUSA
void gp10b_gr_intr_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc);
int gp10b_gr_intr_handle_sw_method(struct gk20a *g, u32 addr,
u32 class_num, u32 offset, u32 data);
@@ -52,4 +53,5 @@ int gp10b_gr_intr_handle_sm_exception(struct gk20a *g,
u32 gpc, u32 tpc, u32 sm,
bool *post_event, struct nvgpu_channel *fault_ch,
u32 *hww_global_esr);
#endif /* CONFIG_NVGPU_HAL_NON_FUSA */
#endif /* NVGPU_GR_INTR_GP10B_H */