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gpu: nvgpu: gv11b: Fix CBC base calculus
On GV11B, CBC base is calculated in similar fashion than it's calculated on dGPUs. Thus, remove gv11b_ltc_cbc_fix_config() as it would incorrectly multiply the CBC base by the LTC count. Bug 2054860 Change-Id: Iaed717161547468c17e12236149d970c497885b3 Signed-off-by: Sami Kiminki <skiminki@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1654506 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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@@ -95,7 +95,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
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.init_comptags = vgpu_ltc_init_comptags,
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.cbc_ctrl = NULL,
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.isr = gv11b_ltc_isr,
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.cbc_fix_config = gv11b_ltc_cbc_fix_config,
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.flush = gm20b_flush_ltc,
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.set_enabled = gp10b_ltc_set_enabled,
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},
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@@ -236,7 +236,6 @@ static const struct gpu_ops gv11b_ops = {
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.init_comptags = gp10b_ltc_init_comptags,
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.cbc_ctrl = gp10b_ltc_cbc_ctrl,
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.isr = gv11b_ltc_isr,
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.cbc_fix_config = gv11b_ltc_cbc_fix_config,
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.flush = gm20b_flush_ltc,
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.set_enabled = gp10b_ltc_set_enabled,
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},
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@@ -187,15 +187,3 @@ void gv11b_ltc_isr(struct gk20a *g)
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/* fallback to other interrupts */
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gp10b_ltc_isr(g);
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}
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u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base)
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{
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u32 val = gk20a_readl(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r());
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if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) == 2)
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return base * 2;
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else if (ltc_ltcs_ltss_cbc_num_active_ltcs__v(val) != 1) {
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nvgpu_err(g, "Invalid number of active ltcs: %08x", val);
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}
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return base;
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}
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@@ -29,6 +29,5 @@ void gv11b_ltc_set_zbc_stencil_entry(struct gk20a *g,
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u32 index);
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void gv11b_ltc_init_fs_state(struct gk20a *g);
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void gv11b_ltc_isr(struct gk20a *g);
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u32 gv11b_ltc_cbc_fix_config(struct gk20a *g, int base);
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#endif
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