Seshendra Gadagottu
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60e3d135de
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gpu: nvgpu: add engine valid check before reading engine status
Before reading engine_status_info, check for NVGPU_INVALID_ENG_ID to
avoid invalid hardware register access.
JIRA NVGPU-3520
Change-Id: I406474b36c9176ce825865ada8ea999a4f9b278e
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2128742
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-06-03 17:55:11 -07:00 |
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Philip Elcan
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78c7e601f8
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gpu: nvgpu: debug: fix MISRA 5.7 violation
MISRA 5.7 requires tag names be unique. Rename the struct
gk20a_debug_output to nvgpu_debug_context to avoid name collision with
the function of the same name.
JIRA NVGPU-3346
Change-Id: I9566b9dc6a7d090e87d9a09f6b8faf688589fbbd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2116877
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-05-16 11:57:32 -07:00 |
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Seema Khowala
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170d7464d6
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gpu: nvgpu: move fifo_gk20a.[ch] to hal/fifo
Move fifo_gk20a struct to fifo.h
Move fifo_gk20a.[ch] to hal/fifo
Add missing includes for fifo subunits.
JIRA NVGPU-2012
Change-Id: I8bf5402bd5a9f8ff9f6a818cee553b57e117f3bc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109012
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-05-02 23:40:42 -07:00 |
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Seema Khowala
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c0cf011600
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gpu: nvgpu: move gk20a_decode_pbdma_chan_eng_ctx_status
Moved from fifo_gk20a.c to common/fifo/fifo.c
gk20a_decode_pbdma_chan_eng_ctx_status
Renamed
gk20a_decode_pbdma_chan_eng_ctx_status ->
nvgpu_fifo_decode_pbdma_ch_eng_status
JIRA NVGPU-2950
Change-Id: I10ec766a28b1b7dabd334bacfb76a6aa14f49fe6
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094651
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-04-16 10:46:02 -07:00 |
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Debarshi Dutta
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61fd020137
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gpu: nvgpu: move engine_status and pbdma_status HAL units to hal/fifo
engine_status and pbdma_status HAL specific units are moved from
common/fifo to hal/fifo.
Jira NVGPU-1315
Jira NVGPU-2950
Change-Id: Ic4eab71bcc53c04f6b855d5eebe919bce57a3494
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2071271
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2019-03-21 04:36:48 -07:00 |
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