Commit Graph

5 Commits

Author SHA1 Message Date
Vedashree Vidwans
e9e9ae9b92 gpu: nvgpu: fix MISRA rule 14.2 for loops
MISRA Rule 14.2 requires for loop to be well-formed. A well-formed for
loop has below requirements:
1. first clause can be empty or should assign value to a single loop
counter
2. second clause should exist and use loop counter or loop control flag.
It should not use any variable modified in the loop body.
3. third cluase should only update loop counter and should not use
objects modified in the loop body.

This modifies for loops to process single loop counter. The patch moves
additional initializations before for loop, conditions at loop start
and variable updates at the end of for loop.

Jira NVGPU-855

Change-Id: I93ccf1ac0677ff355364a718d2d953467f1d9d95
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2108188
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-07 11:37:29 -07:00
Abdul Salam
bc10ef568e gpu: nvgpu: Restructure boardobjgrpmask unit
This patch does the following for boardobjgrpmask unit.
1. Remove unused functions and its pointers.
2. Append public functions with nvgpu.
3. Remove unnecessary inclusion of header files.
4. Make local functions as static.
5. Rename function names to increase readibility.
6. Remove boardobj* from static functions.

Jira NVGPU-1977

Change-Id: Ie6d3bd8f55784d29ae4ba720fb3998487ad2b942
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107167
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-29 11:04:46 -07:00
rmylavarapu
be0eabeb6c gpu:nvgpu: Move nvgpu_clk_pmupstate into nvgpu_pmu
Moved nvgpu_clk_pmupstate structure from gk20a to
nvgpu_pmu.The aim is to have single pmu structure inside
gk20a, that is "nvgpu_pmu" struct and all the global
structures of all units in PMU should be included in
"nvgpu_pmu" struct.

NVGPU-3220

Change-Id: I531aab568a692c55e640ca2c33aa7508b83a9593
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104129
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-26 02:55:02 -07:00
rmylavarapu
55615829e5 gpu: nvgpu: Clean Perf_pstate unit
-Removed 5x verson code as it is no longer used.
-Renamed 5x to 6x as the latest Performance table
version is 0x60.

NVGPU-1958

Change-Id: I1a18a5e89acfbcc36b7032062f587e7be9641842
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099220
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-23 07:14:32 -07:00
rmylavarapu
6e67eec8d5 gpu:nvgpu: Restructure P-state unit
Description:
Present p-state unit handle both pstate boardobj and
initializing all the units. As part of restructuring,
the pstate unit is separated into two units:
1) Perf_pstate: This unit will handle pstate boardobjs.
2) Pmu_pstate: This unit will initialize all the units
which supoort performance states.

Changes:
1) Created pmu_pstate unit.
2) Pstate boardobjs are moved under perf_pstate which
is under perf unit.

NVGPU-1958

Change-Id: I2c428adfe6de4992c9eeda0d4356d30290f6e8a4
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2096339
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-23 07:14:09 -07:00