Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:281:
cert_violation: Casting "ts >> 32" from "unsigned long long" to
"unsigned int" without checking its value may result in lost
or misinterpreted data.
Error: CERT INT31-C:
drivers/gpu/nvgpu/hal/gr/ctxsw_prog/ctxsw_prog_gm20b.c:186:
cert_violation: Casting "enable" from "bool" to "unsigned int"
without checking its value may result in lost or misinterpreted data.
JIRA NVGPU-3410
Change-Id: I4879c8e09d8498bb2377b166035ae0e79adf8870
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119397
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
MISRA rule 11.3 states that a cast shall not be performed between
a pointer to object type and a pointer to a different object type.
The following gr context routines convert a gr context buffer pointer
in the form of a u8 * to a u32 * before referencing the context buffer's
contents:
* gm20b_ctxsw_prog_check_main_image_header_magic
* gm20b_ctxsw_prog_check_local_header_magic
* gm20b_ctxsw_prog_get_num_gpcs
* gm20b_ctxsw_prog_get_num_tpcs
* gm20b_ctxsw_prog_get_extended_buffer_size_offset
* gm20b_ctxsw_prog_get_ppc_info
* gm20b_ctxsw_prog_get_local_priv_register_ctl_offset
Because the gr context buffer pointer starts out as a u32 * the
conversion to a u8 * isn't strictly necessary.
So this patch eliminates the conversion and the 11.3 rule violations
accordingly.
JIRA NVGPU-782
Change-Id: I0d24b539ad6ee8e56318287ce8640764285ed54d
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2102986
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
