Commit Graph

14 Commits

Author SHA1 Message Date
Konsta Hölttä
4acf78dff3 gpu: nvgpu: guard sync cmd hals properly
Make the syncpt and sema wait and incr command HAL ops consistent. Add
CONFIG_NVGPU_SW_SEMAPHORE guards for the semaphore ops. The syncpoint
ops already have CONFIG_TEGRA_GK20A_NVHOST around them.

Delete the dummy syncpt ops. They are not used; the ops are only needed
when the real versions exist.

Jira NVGPU-4548

Change-Id: I30315a67169b31b1d63a0a1a0a4492688db4a2bc
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325100
(cherry picked from commit ed13b286c5fbdbc008ec59172d98ac79e9f2e733)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331337
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
39844fb27c gpu: nvgpu: hide priv cmdbuf mem writes
Add an API to append data to a priv cmdbuf entry. Hold the write pointer
offset internally in the entry instead of having the user keep track of
where those words are written to.

This helps in eventually hiding struct priv_cmd_entry from users and
provides a more consistent interface in general. The wait and incr
commands are now slightly easier to read as well when they're just
arrays of data.

A syncfd-backed prefence may be composed of several individual fences.
Some of those (or even a fence backed by just one) may be already
expired, and currently the syncfd export design releases and nulls
semaphores when expired (see gk20a_sync_pt_has_signaled()) so for those
the wait cmdbuf is appended with zeros; the specific function is for
this purpose.

Jira NVGPU-4548

Change-Id: I1057f98c1b5b407460aa6e1dcba917da9c9aa9c9
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2325099
(cherry picked from commit 6a00a65a86d8249cfeb06a05682abb4771949f19)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2331336
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
6202ead057 gpu: nvgpu: split sema sync hal to wait and incr
Instead of one HAL op with a boolean flag to decide whether to do one
thing or another entirely different thing, use two separate HAL ops for
filling priv cmd bufs with semaphore wait and semaphore increment
commands. It's already two ops for syncpoints, and explicit commands are
more readable than boolean flags.

Change offset into cmdbuf in sem wait HAL to be relative to the cmdbuf,
so the HAL adds the cmdbuf internal offset to it.

While at it, modify the syncpoint cmdbuf HAL ops' prototypes to be
consistent.

Jira NVGPU-4548

Change-Id: Ibac1fc5fe2ef113e4e16b56358ecfa8904464c82
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323319
(cherry picked from commit 08c1fa38c0fe4effe6ff7a992af55f46e03e77d0)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328409
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2020-12-15 14:13:28 -06:00
Konsta Hölttä
b3d16b23d5 gpu: nvgpu: extract priv cmdbuf from channel.c
Move private command buffer related functionality to priv_cmdbuf.c. This
is used only for kernel mode submits, so it makes sense to group it out,
and the priv cmdbuf stuff is used also by things that don't care about
channels.

Jira NVGPU-4548

Change-Id: Idbb42e3ed3984e16c654bb9aa2b7564b780048a4
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2323146
(cherry picked from commit bb67bfc7ab8e87236f31bc4f6c80dab042609f21)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2328406
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2020-12-15 14:13:28 -06:00
Sagar Kamble
ea09ef92b5 gpu: nvgpu: conditional compilation of nvhost code
There were few more nvhost related references unprotected by the config
flag. Fix those.

Bug 2834141

Change-Id: Id7d94e3e6fa471f02697d121b557884c7287c26e
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2306437
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GVS: Gerrit_Virtual_Submit
2020-12-15 14:13:28 -06:00
Adeel Raza
26af1c2270 gpu: nvgpu: MISRA integer fixes
Apply various MISRA integer related fixes. Some fixes simply required
adding a "U" suffix to integer constants. Other fixes were more
complicated and required breaking up complex composite expressions into
multiple smaller expressions.

JIRA NVGPU-3873

Change-Id: Id8a08a17d1cf9e20193bd3e4f2d4104774d81767
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2262189
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2020-12-15 14:10:29 -06:00
Debarshi Dutta
25adc8d587 gpu: nvgpu: add UT coverage for sync unit
This patch adds full branch coverage for the functions
nvgpu_channel_sync_create and nvgpu_channel_sync_destroy.

Jira NVGPU-913

Change-Id: Iab9922ccd57873f0aab452805ea506b4b2601d5d
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2254954
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2020-12-15 14:10:29 -06:00
Adeel Raza
252ddc4f05 gpu: nvgpu: add coverity whitelisting support
Add macros for whitelisting coverity violations. These macros use pragma
directives. The pragma directives and whitelisting macros are only
enabled when a coverity scan is being run.

The whitelisting macros have been added to a new header called
static_analysis.h. The contents of safe_ops.h (CERT C safe ops) have
been moved into static_analysis.h because this will be the new header
for static analysis related macros/defines/etc.

JIRA NVGPU-3820

Change-Id: I9c63f20f670880b420415535738034619314b7c3
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180600
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2020-12-15 14:05:52 -06:00
Vedashree Vidwans
58f174b29e gpu: nvgpu: fix MISRA errors nvgpu.hal.sync
Rule 2.2 doesn't allow unused variable assignments. The reason is
presence of unused variable assignments may indicate error in program's
logic.
Rule 7.2 requires all unsigned numeric literals to use a "u"/"U" suffix.
Rule 8.3 requires all functions and prototypes to have same parameter
names and type qualifier.
Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
Rule 12.2 requires right hand operand of shift operator to be within
range 0 to 1 less than width of left hand operand.
This patch fixes above mentioned rules in hal/sync/syncpt_cmdbuf_gv11b.c

Jira NVGPU-3884

Change-Id: Ia375b2e08f48bc82fb641a48f4f5a5a75455217d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168708
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
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2019-08-13 18:06:31 -07:00
Debarshi Dutta
69ef86e627 gpu: nvgpu: move safe code HAL files to fusa
This patch moves all the safe static and non-static functions as well
as its dependencies such as static declared structs into files with
_fusa.c extension. If the original file is left with no functions
remaining then the file is deleted.

Added changes in Makefile, Makefile.sources, nvgpu-hal-new.yaml for
compilation.

Jira NVGPU-3690

Change-Id: I81af67c308705faf8a681df63a6778e7de2076cf
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146761
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
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2019-07-03 02:46:15 -07:00
Debarshi Dutta
db80498307 gpu: nvgpu: add CONFIG_NVGPU_KERNEL_MODE_SUBMIT flag
Following are removed for safety build by adding
CONFIG_NVGPU_KERNEL_MODE_SUBMIT flag.

1) HAL ops in g->ops.sync.syncpt

add_wait_cmd
get_wait_cmd_size
add_incr_cmd
get_incr_cmd_size
get_incr_per_release

2) g->ops.sync.sema is removed in its entirety and contains the
following ops.

3) The following files are compiled out using the above flag.
hal/sync/sema_cmdbuf_gk20a.c
hal/sync/sema_cmdbuf_gv11b.c

Jira NVGPU-3479

Change-Id: I99ae6913e5fe5707ff9a3e2cf06cee8710def7cc
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2130352
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2019-06-30 22:05:12 -07:00
Vaibhav Kachore
854e861ad0 gpu: nvgpu: fix CERT-C violations
This patch fixes following CERT-C violations for power management unit:
- CERT INT31-C

NVGPU-3403

Change-Id: I4eb2374cc720c6d0bb81d6a4d9750348d4e5a670
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2117659
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2019-05-22 03:16:56 -07:00
Debarshi Dutta
17486ec1f6 gpu: nvgpu: rename tsg_gk20a and channel_gk20a structs
rename struct tsg_gk20a to struct nvgpu_tsg and rename struct
channel_gk20a to struct nvgpu_channel

Jira NVGPU-3248

Change-Id: I2a227347d249f9eea59223d82f09eae23dfc1306
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2112424
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2019-05-06 02:56:53 -07:00
Thomas Fleury
e69b5f75ba gpu: nvgpu: move sync cmdbuf to hal/sync
Moved
- common/sync/sema_cmdbuf_gk20a.c -> hal/sync/sema_cmdbuf_gk20a.c
- common/sync/sema_cmdbuf_gk20a.h -> hal/sync/sema_cmdbuf_gk20a.h
- common/sync/sema_cmdbuf_gv11b.c -> hal/sync/sema_cmdbuf_gv11b.c
- common/sync/sema_cmdbuf_gv11b.h -> hal/sync/sema_cmdbuf_gv11b.h
- common/sync/syncpt_cmdbuf_gk20a.c -> hal/sync/syncpt_cmdbuf_gk20a.c
- common/sync/syncpt_cmdbuf_gk20a.h -> hal/sync/syncpt_cmdbuf_gk20a.h
- common/sync/syncpt_cmdbuf_gv11b.c -> hal/sync/syncpt_cmdbuf_gv11b.c
- common/sync/syncpt_cmdbuf_gv11b.h -> hal/sync/syncpt_cmdbuf_gv11b.h

Updated makefiles and #include directives.

Jira NVGPU-1984

Change-Id: I5df008512a9243572081a89310d12a77c2354924
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101322
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2019-04-22 23:54:35 -07:00