4 Commits

Author	SHA1	Message	Date
ajesh	0030dc3eb4	gpu: nvgpu: fix MISRA violations in Posix unit ... Fix violations of MISRA rule 5.4 in Posix unit. JIRA NVGPU-6534 Change-Id: I9471e5fca913ca8cc19403998fdbe5450fb49879 Signed-off-by: ajesh <akv@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2488184 (cherry picked from commit f9bc21ca8d96e9c531a1b0077cfe1e78502e7ee5) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2491855 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2021-03-04 00:37:15 -08:00
Vedashree Vidwans	c3f7d9a3b0	gpu: nvgpu: fix MISRA 17.7 in common.sec2.allocator ... MISRA Rule 17.7 doesn't allow return value of a function to be ignored. This patch checks return value of nvgpu_allocator_init function and returns error to the sec2_process_init_msg() function. Jira NVGPU-3321 Change-Id: Ie3eb1b5f9312e178f8f3e6de310d768c3ac3e220 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2123221 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Philip Elcan <pelcan@nvidia.com> Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-05-22 16:44:59 -07:00
Vedashree Vidwans	8d325e9db1	gpu: nvgpu: re-architect nvgpu allocator functions ... Currently, buddy, page and bitmap allocators have individual init() functions. This patch creates common nvgpu_alloc_allocator_init() function to trigger the individual functions based on allocator type argument. This makes writing requirements for the allocators easier. Jira NVGPU-991 Change-Id: If94e3496f46f036460ef9f1831852e6fc19d3a0b Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2097962 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-24 19:14:42 -07:00
Sagar Kamble	e848e9dfb8	gpu: nvgpu: prepare sec2 msg, allocator units ... SEC2 message handling unit can't be part of command handling unit as it creates circular dependencies with the SEC2 tasks (ACR bootstrap) SEC2 allocator unit shall encompass DMEM allocator and other allocators used by SEC2. JIRA NVGPU-2075 Change-Id: Ic2b8204d8225f2056785f035cbecdb776a9ecfe9 Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2085749 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2019-04-10 09:26:14 -07:00