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Author SHA1 Message Date
Tejal Kudav
4dcfbc19de gpu: nvgpu: Trigger quiesce on spurious FBPA intr 
In Bug 200588835, the spurious FBPA interrupts are seen on couple
of boards. These interrupts were found to be EDC (Error detection
and Correction) interrupts which are triggered due to ECC errors.
The EDC registers are not exposed to the driver, so the interrupt
status register cannot be cleared; resulting in interrupt storm.
Also, it was concluded that only bad HW can cause this failure
scenario. So, in the ISR for FBPA interrupts, get the GPU into
quiesce state as we don't expect the GPU to be in usable state post
such unrecoverable errors.

Adapt the quiesce code for Linux build too.
1. On Linux, we cannot exit the nvgpu process after quiesce like we
   do on QNX. So, add nvgpu_disable_irqs() call to quiesce
   implementation which is done as part of process exit handler on
   QNX. Masking interrupts which is already done as part of quiesce
   would be sufficient in most cases, but to be fail-safe
   disable_irqs too.
3. Also, the IOCTL code looks at g->sw_ready, hence add
   nvgpu_start_gpu_idle() to set g->sw_ready to false along with
   setting NVGPU_DRIVER_IS_DYING = true.

We expect the nvgpu_sw_quiesce() call to finish before quiesce thread
wakes up from 50ms sleep. Hence, critical step like
nvgpu_start_gpu_idle() is added to nvgpu_sw_quiesce(), whereas the
somewhat redundant disable IRQs call is added to quiesce thread.

nvgpu_fifo_quiesce() was called twice by mistake; remove one of the
them.

Bug 2919899
Bug 200588835

Change-Id: I9beec688c2e1c0d8dfc1327ddf122684576f8684
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2354537
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
6778fc9eb6 gpu: nvgpu: remove fence validity checks 
The valid flag in struct nvgpu_fence_type is not very useful. It's set
when a fence is created on an allocated object and read in these three
scenarios:

- nvgpu_fence_install_fd() after a submit, if the submit was successful.
  A successful submit implies that a post fence exists.
- nvgpu_fence_wait() for a copyengine job when synchronizing the ce
  ringbuffer or when waiting for vidmem clears. In these cases the fence
  is also clearly always valid.
- nvgpu_fence_is_expired() when testing whether a tracked job has
  completed. Such jobs cannot exist without post fences that are
  mandatory for tracking, so the fence must exist.

Remove the valid flag. Remove also the other init checks from the above
functions; they're equally unused and confusing implying that such calls
would be acceptable, causing sloppy code at best.

Jira NVGPU-5248
Jira NVGPU-5493

Change-Id: I52c5be1569b343024d2626bd9577f87b46064fba
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
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 2020-12-15 14:13:28 -06:00
mkumbar
2dfa74c831 gpu: nvgpu: ACR interface update 
FALCON_ID_END is used in ACR lsf_ucode_desc interface to allocate
space for dependency map but now more number of  FALCON’s supported
which will cause wrong allocation for dependency map, so required to
have its definition.

JIRA NVGPU-5462

Change-Id: Idaaa24ea1d2767a0b4ef44b1376239f945e39912
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2357747
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
4e241d5974 gpu: nvgpu: adapt to generic syncpt api 
Use the nvhost sync fence APIs that do not require knowledge about the
sync fence version. Nvhost exports an opaque nvhost_fence type with a
common interface for both legacy and stable sync fences.

Delete the syncfd-specific nvhost wrappers. They exist only on Linux, so
having them in the nvhost wrapper layer is just a hassle. The os fence
interface is already one wrapper.

Jira NVGPU-5386

Change-Id: I3849db3684c7be8f37cf53971347f26247a52d6c
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Tejal Kudav
3a11bd69e7 Revert "gpu: nvgpu: modify nvgpu_writel check and loop" 
This reverts commit c100ac23455d450a7046c62915014111a0aa2e70.

Bug 3009270

Change-Id: I1db1acac63c841b5383d75ec674fdc2160a0c84d
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2356076
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 2020-12-15 14:13:28 -06:00
Dinesh
290911618a gpu: nvgpu: Check for vidmem failure 
This is added to check the vidmem init failure during gpu
initialization.

JIRA NVGPU-5389

Change-Id: I0111f302058e171031407c88804ba30c2509fabc
Signed-off-by: Dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2352916
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
6cbc174fc2 gpu: nvgpu: avoid channel wdt ifdefs 
Implement empty stubs of the channel watchdog functions for when
watchdog is disabled from build. Add some forward declarations that were
missing. Now most call sites don't need #idefs for the build flag.

Add error checks for the wdt alloc failure.

Jira NVGPU-5494
Jira NVGPU-5493

Change-Id: I2d42e8ab4c5e045cd280b2e1f254396127bd154b
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2352050
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
2ad015f7a5 gpu: nvgpu: modify nvgpu_writel check and loop 
Currently, nvgpu_writel_loop() writes to a register and immediately
checks if register value is updated. It might take some time for
hardware registers to get updated with value written by software.
Modify nvgpu_writel_loop() to accept number of retries to check if
register value is updated and assert with nvgpu_assert().
Also, move nvgpu_writel_loop() to common code and use generic
nvgpu_readl() and nvgpu_writel() APIs.

JIRA NVGPU-5490

Change-Id: Iaaf24203a91eee3d05de7d0c7dea18113367de5f
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2348628
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 2020-12-15 14:13:28 -06:00
mkumbar
c43e3e4aeb gpu: nvgpu: acr: add fecs/gpccs sig files read for next dgpu 
add fecs/gpccs sig file read for next dgpu.

JIRA NVGPU-5461

Change-Id: Ib135dab8961c53d62fb7a95e378eba4c81d729a2
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2354622
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 2020-12-15 14:13:28 -06:00
Sami Kiminki
36a488392f gpu: nvgpu: add PDI reporting for vgpu 
Read the PDI from vgpu constants.

Bug 2957580
Bug 2992739

Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Change-Id: Ief2edeaaa26e284707792f13d218c511fef073af
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2351214
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
fc5b45ea83 gpu: nvgpu: move init_ltc_support sequence 
Currently, ltc fs_state is initialized during ltc init support. However,
ltc cbc_param and cbc_param2 registers do not seem to be providing
correct data if ltc.init_fs_state is called before fb.init_fs_state.
- Create fb.init_fb_support hal to initialize fb.
- Trigger init_fb_support before init_ltc_support.

Bug 2969956
Bug 2957808
JIRA NVGPU-4666

Change-Id: I54d697d27b9d9c6318c4ef459d215b6f82cd5571
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Alex Waterman
2a3bb9107f gpu: nvgpu: rename <nvgpu/top.h> to <nvgpu/device.h> 
top.h is a description of "devices" available on the GPU. As such
rename this header to device.h.

device.h will ultimately be a unit of actual C code that will rely
on the top HAL to fill a device list.

JIRA NVGPU-5421

Change-Id: If6e4a537d2209e429a678761a34713723da7a00a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2319648
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 2020-12-15 14:13:28 -06:00
tkudav
957b19092f gpu: nvgpu: Enable Quiesce on all builds 
Make Recovery and quiesce co-exist to support quiesce state
on unrecoverrable errors. Currently, the quiesce code is wrapped
under ifndef CONFIG_NVGPU_RECOVERY. Isolate the quiesce code from
recovery config, thereby enabling it on all builds.

On Linux, the hung_task checker(check_hung_uninterruptible_tasks()
in kernel/hung_task.c) complains that quiesce thread is stuck for
more than 120 seconds.

INFO: task sw-quiesce:1068 blocked for more than 120 seconds.

The wait time of more than 120 seconds is expected as quiesce
thread will wait until quiesce call is triggered on fatal
unrecoverable errors. However, the INFO print upsets the
kernel_warning_test(KWT) on Linux builds. To fix the failing
KWT, change the quiesce task to interruptible instead of
uninterruptible as checker only looks at uninterruptible tasks.

Bug 2919899
JIRA NVGPU-5479

Change-Id: Ibd1023506859d8371998b785e881ace52cb5f030
Signed-off-by: tkudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2342774
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
8778aa531d gpu: nvgpu: netlist: correct info for generic regions 
There is an issue with reading u32 data for generic regions.
The u8 pointer dereference copying only u8 data instead of
u32 data. Legacy code is not using this data, so the issue
is not caught earlier. Now using nvgpu_memcpy to copy all
bytes of u32 data.

Bug 2986531

Change-Id: Ib23c76cd1ce77e3a2f882940b11703391a11f99d
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2348593
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
16fb7654a5 gpu: nvgpu: isolate channel watchdog unit 
Move the definition of struct nvgpu_channel_wdt to watchdog.c. Adjust
users of it to access it via an unified interface instead of poking
directly at the channel internals.

Jira NVGPU-5494

Change-Id: Ie11826e6732a8b98e72c4f81dd06bd7e49848121
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2345935
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
21e02878f4 gpu: nvgpu: move wdt code out of channel.c 
Cut and paste the existing channel watchdog functions to another file
for better isolation of units.

Jira NVGPU-5494

Change-Id: Id437f0939e69a4a8b495eaee164c4d7a9f283fa9
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2345934
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
2d94863cae gpu: nvgpu: move is_tpc_addr and get_tpc_num to common 
gr.is_tpc_addr() and gr.get_tpc_num() are chip agnostic hals. Move these
hals to common code.

Jira NVGPU-5504

Change-Id: I50fa7ac876c8667de42df1830bd412b412538508
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Sami Kiminki
23cda4f4a9 gpu: nvgpu: add PDI for TU104 (Linux) 
Add reporting for the per-device identifier (PDI) in the Linux GPU
characteristics. Implement PDI read for TU104.

Bug 2957580

Signed-off-by: Sami Kiminki <skiminki@nvidia.com>
Change-Id: I6ac0e4f74378564d82955b431d4c1fd6c0daeb13
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2346933
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Alex Waterman
6b1302f23c gpu: nvgpu: Reduce linux debug log spew 
Currently when nvgpu prints debug information for something like an MMU
fault the result includes a lot of usless boiler plate logging spew. In
some cases this can be helpful in identifying where the log message came
from in the nvgpu code base. However, for debug spews from faults, the
viewer of that info does not care which function printed the log (for
example).

Instead having a fast and readable debug dump is more valuable. So to
that end, add a special debug dump printing function that does not use
the normal log format. Instead, it prints only a breif prefix to use as
a grep search query. The new print out is listed below.

Since often the kernel logs are impressively long and obtuse, having a
clear debug search string can be helpful. With this log format, one can
simply do:

  $ grep __$CHIP__ kernel.log

And find any debug logs for the desired chip.

New log format - collected on a gv11b under L4T running
`nvgpu_submit_mmu_fault':

[   32.005793] nvgpu: 17000000.gv11b      gv11b_fb_mmu_fault_info_dump:311  [ERR]  [MMU FAULT] mmu engine id:  32, ch id:  511, fault addr: 0x1000, fault addr aperture: 0, fault type: invalid pde, access type: virt read,
[   32.006137] nvgpu: 17000000.gv11b      gv11b_fb_mmu_fault_info_dump:320  [ERR]  [MMU FAULT] protected mode: 0, client type: hub, client id:  host, gpc id if client type is gpc: 0,
[   32.006417] nvgpu: 17000000.gv11b                nvgpu_rc_mmu_fault:296  [ERR]  mmu fault id=0 id_type=1 act_eng_bitmask=00000000
[   32.007125] __gv11b__ Channel Status - chip gv11b
[   32.007128] __gv11b__ ---------------------------
[   32.007241] __gv11b__ 511-gv11b, TSG: 0, pid 955, refs: 2, deterministic:
[   32.007364] __gv11b__ channel status:  in use pending busy
[   32.007509] __gv11b__ RAMFC : TOP: 8000000000001000 PUT: 0000000000001030 GET: 0000000000001000 FETCH: 0000600000001000HEADER: 60400000 COUNT: 00000000SEMAPHORE: addr 0000000000000000payload 0000000000000000 execute 00000000
[   32.007601] __gv11b__
[   32.008696] __gv11b__
[   32.008700] __gv11b__ PBDMA Status - chip gv11b
[   32.008894] __gv11b__ -------------------------
[   32.013477] __gv11b__ pbdma 0:
[   32.017840] __gv11b__   id: -1 - [channel] next_id: - -1 [channel] | status: invalid
[   32.020992] __gv11b__   PBDMA_PUT 0000000000001030 PBDMA_GET 0000000000001000
[   32.029037] __gv11b__   GP_PUT    00000001  GP_GET  00000001  FETCH   00000001 HEADER 60400000
[   32.036386] __gv11b__   HDR       00000000  SHADOW0 00001000  SHADOW1 80003000
[   32.044787] __gv11b__ pbdma 1:
[   32.051964] __gv11b__   id: -1 - [channel] next_id: - -1 [channel] | status: invalid
[   32.055099] __gv11b__   PBDMA_PUT 0000000042003200 PBDMA_GET 00000050728bc914
[   32.062997] __gv11b__   GP_PUT    00000000  GP_GET  2080a000  FETCH   00000000 HEADER e1850010
[   32.070424] __gv11b__   HDR       00110000  SHADOW0 02000000  SHADOW1 10000004
[   32.078652] __gv11b__ pbdma 2:
[   32.085913] __gv11b__   id: -1 - [channel] next_id: - -1 [channel] | status: invalid
[   32.088973] __gv11b__   PBDMA_PUT 00000021040c0004 PBDMA_GET 0000000140020000
[   32.096502] __gv11b__   GP_PUT    00000000  GP_GET  8080a440  FETCH   00000000 HEADER 61400040
[   32.103679] __gv11b__   HDR       14000010  SHADOW0 00000000  SHADOW1 00000400
[   32.112336] __gv11b__
[   32.119860] __gv11b__ gv11b eng 0:
[   32.122119] __gv11b__ id: -1 (channel), next_id: -1 (channel), ctx status: invalid
[   32.125807] __gv11b__
[   32.135954] __gv11b__ gv11b eng 1:
[   32.135958] __gv11b__ id: -1 (channel), next_id: -1 (channel), ctx status: invalid
[   32.139457] __gv11b__
[   32.149945] __gv11b__ gv11b eng 2:
[   32.149950] __gv11b__ id: -1 (channel), next_id: -1 (channel), ctx status: invalid
[   32.153543] __gv11b__
[   32.163598] __gv11b__ gv11b eng 3:
[   32.163601] __gv11b__ id: -1 (channel), next_id: -1 (channel), ctx status: invalid
[   32.167278] __gv11b__
[   32.177076] __gv11b__
[   32.186145] nvgpu: 17000000.gv11b       nvgpu_tsg_set_ctx_mmu_error:492  [ERR]  TSG 0 generated a mmu fault
[   32.189443] nvgpu: 17000000.gv11b     nvgpu_set_err_notifier_locked:140  [ERR]  error notifier set to 31 for ch 511

JIRA NVGPU-5541

Change-Id: Iad60adfab5198ee11dd2ec595f2422ea541b7a2a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2349166
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Alex Waterman
5d06a59bc5 gpu: nvgpu: Cleanup uart and debugfs debug prints 
The gk20a_debug_dump() function implicitly adds a newline since it
uses nvgpu_err() under the hood (for uart destined prints). For the
seq_file destined writes it does not so there is an annoying inconsistency.

Remove the newline that many of the gk20a_debug_dump() calls add and add
the newline to the (now) seq_printf() call. This reduces the length of
debug dump logs and speeds them up - UART is _very_ slow after all.

Also cleanup some formatting issues in the various debug prints I
happened to notice.

JIRA NVGPU-5541

Change-Id: Iabf853d5c50214794fc4cbb602dfffabeb877132
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2347956
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Antony Clince Alex
50dcfe1637 gpu: nvgpu: update fb unit ecc init, handling 
The ecc init, handling for the fb unit is refactored to improve reusability
for nvgpu-next.

The following changes have been done:
- fb.ecc:
  This is a new subunit within fb and contains the following functions:
  - init: Moved from fb.fb_ecc_init.
  - free: Moved from fb.fb_ecc_free.
  - l2tlb_error_mask: Fetch bit mask for corrected, uncorrected errors supported
    by the unit.
- fb.intr:
  This unit has been updated to include the following ecc interrupt, error
  handlers:
  - handle_ecc: Top level interrupt handler for fb ecc errors.
  - handle_ecc_l2tlb: Handle errors within l2tlb memory.
  - handle_ecc_hubtlb: Handle errors within hubtlb memory.
  - handle_ecc_fillunit: Handle errors within fillunit memory

Jira: NVGPU-5032

Change-Id: I1a26c1823eb992e0e0175250b969f1186dff6e62
Signed-off-by: Antony Clince Alex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333271
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 2020-12-15 14:13:28 -06:00
Abdul Salam
d339d9ed33 gpu: nvgpu: segregate clk_mon from clk unit. 
As a part of refactoring this CL removes clk_mon unit from
clk unit.
Clk_mon is used for monitoring of clk and it is an independent unit.
This patch does the following.
*Move the clk_mon struct from clk.h to clk_mon_tu104.h
*create a new clk_mon gpu_ops and assign clk_mon specific ops there.
*Move all the function to clk_mon_tu104.c
*Update the yaml file

NVGPU-4689

Change-Id: Ia72bf28a93ce9a7936c277076f365c4b6593b032
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336230
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2020-12-15 14:13:28 -06:00
mkumbar
91af7efd23 gpu: nvgpu: enable ACR support for NEXT dGPU 
-Enabled ACR support for NEXT dGPU
-Blob creation & boot strap of LSPMU support skipped by ACR
 by checking flag "support_ls_pmu", lspmu support is not
 required until PSTATE support is enabled.

JIRA NVGPU-5461

Change-Id: I5a4c688926ca1c55aeb4cbbb9668c55bb35f9119
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2344582
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Abdul Salam <absalam@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
2077df9b1a gpu: nvgpu: use set_syncpt only with nvhost 
nvgpu_channel_set_syncpt() is not useful if nvhost and thus syncpts are
missing and semaphores are used for synchronization. Require
CONFIG_TEGRA_GK20A_NVHOST to be set for the set_syncpt hal.

Jira NVGPU-5496

Change-Id: Ief8b4a0fb29af631817aba55c04181b1a360ce56
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2344064
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
b6bf13290e gpu: nvgpu: alloc correct prealloc buffer sizes 
The trivial ringbuffer implementation in channel job list and priv cmd
buffers acts such that the buffer is full when the number of inserted
entries in it is one less than allocation size, similarly to the
hardware gpfifo. Take this into account when allocating the job tracking
resources: previously the allocation has been off-by-one too small.

Jira NVGPU-5492

Change-Id: If7bfd4919daa5b0328394ca289d5692c0d2b4f5f
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2342129
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
mkumbar
9c2a0ce72d gpu: nvgpu: enable falcon sw init for NEXT dGPU 
Enable GSP, SEC2, NVDEC, PMU, FECS & GPCCS engines Falcon s/w
support for NEXT dGPU.

JIRA NVGPU-5464

Change-Id: I5398d4b0331c4ff59e00d0dd1857baa84db609d2
Signed-off-by: mkumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339669
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d916e85171 gpu: nvgpu: incr sync once submit is ready to go 
Split out the max value increment and syncpt interrupt registration out
of nvgpu_channel_sync_incr*(). This API is called in the submit path to
prepare buffers and tracking resources, but later on in the submit path
errors can still occur so that the increment wouldn't happen (unless
artificially forced by sw).

The increment and irq registration cannot easily be undone and it makes
more sense to do these at the moment when the prepared job is finally
ready, so add a new nvgpu_channel_sync_mark_progress() API to be called
later in the submit path to signal that progress shall eventually happen
on the sync. Without this, the max value would stay too large after an
unsuccessful submit until the channel gets closed.

The sync object (syncpt or semaphore) is always exclusively owned by the
channel that allocated it, so nonatomically reading the max value first
in sync_incr() and incrementing it later in mark_progress() is racefree;
all submits per channel are serialized.

Change the channel syncpoint to client managed from host managed so that
nvhost-exported sync fences behave correctly with the temporary state
where the fence threshold is over the max value. Ideally we'd always
track nvgpu-owned syncpts' max values internally, but this is enough for
now.

Jira NVGPU-5491

Change-Id: Idf0bda7ac93d7f2f114cdeb497fe6b5369d21c95
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340465
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Richard Zhao
f73d035983 gpu: nvgpu: vgpu: add vgpu_css_init 
Added vgpu_css_init to setup ivm at init time.

Background:
vgpu_css_reserve_mempool was called at runtime in many places without any lock.
To avoid racing, the patch moves it to init time and rename it to vgpu_css_init.

Bug 200598546

Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Change-Id: I4c7794ee7151fc604643f94700d5b986472b2e71
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336905
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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Reviewed-by: Aparna Das <aparnad@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
a039261724 gpu: nvgpu: add gr.process_context_buffer_priv_segment gops 
1. Add below gr gops to process context buffer's priv segment.
int (*process_context_buffer_priv_segment)(struct gk20a *g,
					 enum ctxsw_addr_type addr_type,
					 u32 pri_addr,
					 u32 gpc_num, u32 num_tpcs,
					 u32 num_ppcs, u32 ppc_mask,
					 u32 *priv_offset);
Update all chips to use gr_gk20a_process_context_buffer_priv_segment()
as new gr hal.
2. Add and use ppc, tpc and etpc count functions to retrieve total count.

Bug 2960720
JIRA NVGPU-5502

Change-Id: I6cec36c323ff49ded853cd5cbfd9e0a28602b8ed
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340372
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Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
Tested-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2020-12-15 14:13:28 -06:00
Konsta Hölttä
a629b48013 gpu: nvgpu: split channel sema wakeup function 
Extract the functionality to post semaphore signals to one channel into
a separate function for readability.

Jira NVGPU-5491

Change-Id: Ib5e8d34f42a64c253b3b3b8cb9e2c5dd2656fd1f
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340466
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
23d6b36101 gpu: nvgpu: add dma_fence semaphore support 
Support exporting and importing semaphore-based synchronization with the
stable dma-fence API. The "Android" sync fence API used until now is
deprecated.

The Android sync framework is still kept as the default.

Jira NVGPU-5353

Change-Id: I9e57947adeb4d2ef5d59135ed7d008553c44f97c
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336119
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 2020-12-15 14:13:28 -06:00
Seshendra Gadagottu
3bd0430aa8 gpu: nvgpu: for nvgpu-next do not reset grce engines twice 
NVGPU_ENGINE_GRCE engines are getting reset twice, once in
nvgpu_init_prepare_hw() and other time in nvgpu_ce_init_support().

To avoid this, remove NVGPU_ENGINE_GRCE engines reset from
nvgpu_init_prepare_hw.

JIRA NVGPU-5288

Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Change-Id: Ic03dbff0a74e973ba423abfa004e49bdd8e451f7
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336450
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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Reviewed-by: Alex Waterman <alexw@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Konsta Hölttä
d44ed9d3a8 gpu: nvgpu: rollback gpfifo on error 
Submitting new work may fail in the middle of writing the gpfifo
entries. Undo the increments on the gp_put shadow pointer in case of
error to avoid submitting wrong data during the next submit.

Jira NVGPU-5491

Change-Id: I064eaac8773b24da0a56db79ac6bfd07c008da03
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340464
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Automatic_Commit_Validation_User
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
f388b1f596 gpu: nvgpu: simplify cmdbuf construction in submit 
Split out the wait cmd and incr cmd setup work in submit path to
separate functions to minimize cyclomatic complexity and to increase
readability.

Jira NVGPU-5491

Change-Id: I7dfabd2de287ae10aaae9fb8d4d85d752db8631c
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2340463
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Dinesh
b79bee9cea gpu: nvgpu: CCM reduction for vidmem clear 
This is added to make a common function  nvgpu_vidmem_clear_fence_wait
that can be used by multiple callers. This helps to reduce CCM and
code duplication in vidmem unit.

JIRA NVGPU-990

Change-Id: I3a7090588abda68900849443f6a8fa1bfa246bf4
Signed-off-by: Dinesh <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332691
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
3875c0825f gpu: nvgpu: avoid sema/channel dependencies 
Move the per-channel hw semaphore object to be owned by the channel sync
(just like with syncpoints, too). Store just the channel ID in the hw
sema for debug prints to get rid of sema->channel dependencies. Make
nvgpu_semaphore_alloc() take a hw sema instead of a channel.

Fix up some channel-related documentation that has been incorrect.

Jira NVGPU-5353

Change-Id: I04d49da3aac50a4cea32e7393f48e6f85a80ca0d
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339931
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 2020-12-15 14:13:28 -06:00
Abdul Salam
97de1ba74d gpu: nvgpu: Use unified struct to store slave freq 
Instead of using multiple struct use a single nvgpu_clk_slave_freq
to store the slave freq of gpcclk.
With this patch single struct can be used by both clk_arb and clk_domain.
This will remove nvgpu_set_fll_clk struct as nvgpu_clk_slave_freq serves
the purpose.

NVGPU-4692

Change-Id: Ie45d63e4376b83e153a9aa75e2c4631c6dad857b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2339213
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 2020-12-15 14:13:28 -06:00
rmylavarapu
700bd83b41 gpu: nvgpu: Rename/clean boardobj unit 
-Removed unwanded boardobj includes
-Renamed functions as struct as per usage

NVGPU-4484

Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Change-Id: I792a4b64075d5e87f911c1073717dbe7107227a1
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335991
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
8e545ef04b gpu: nvgpu: Fix boardobj allocation size 
In current implementation we are allocating boardobj
in nvgpu_boardobj_construct_super for all units and assigning
that pointer to boardobj type, as the size differe for different
units assigning the boardobj pointer to a common type will
give violations. Fixing them by allocating mem a head
and later call construct_super for elements initialization.

NVGPU-4484

Change-Id: I9b5ed1a6d8418fec48a29eee38d55fc7d83fcfab
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335989
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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 2020-12-15 14:13:28 -06:00
rmylavarapu
0115c26f1b gpu: nvgpu: Boardobj lite unit refactor 
As boardobj unit is used only in PMU, the plan is to move
all the boardobj related functions/structures and Macros
to boardobj specific folders. This will remove unnecessary
usage of boardobj outside PMU.

NVGPU-4484

Change-Id: I9f0fda32e6affd1fce218eb0ac638a9dfc8b99c3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2335986
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
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GVS: Gerrit_Virtual_Submit
 2020-12-15 14:13:28 -06:00
Konsta Hölttä
b8f398f6a7 gpu: nvgpu: clean up struct priv_cmd_entry 
The valid flag is no longer useful as the lifetime of priv cmd entries
is clearer than before. Delete it. Delete also the stored gva that can
be calculated from the nvgpu_mem plus offset.

Jira NVGPU-4548

Change-Id: Ibf322acbb2ab1a454e9b644af24c02d291b75633
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
(cherry picked partially from commit
b9f6512e803873aaa92218dcbc090ff31a4f9c50)
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 2020-12-15 14:13:28 -06:00
Seema Khowala
cfc5bac059 gpu: nvgpu: add assert in nvgpu_writel_check 
nvgpu_writel_check outputs dbg message if updated read value
does not match with requested write value. Change dbg message to
error message.
Use BUG_ON for write mismatch as failure to update h/w register
is a bug and tells s/w to either add fixed delay or use timeout
to check for updated register value.

JIRA NVGPU-5490

Change-Id: Ib11b7862d2990a56259d2f8c10d75c12c84bae5d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2338004
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
e5b23f33b9 gpu: nvgpu: add internal CONFIG_SYNC wrapper 
The sync file support in Linux has been stabilized and the new config is
called CONFIG_SYNC_FILE. Even if maybe not so intended, both the
stabilized version and the legacy CONFIG_SYNC can coexist; to begin with
supporting the stabilized version, add CONFIG_NVGPU_SYNCFD_ANDROID and
CONFIG_NVGPU_SYNCFD_NONE as choice configs of which one will be set. A
later patch will extend this with a choice for CONFIG_SYNC_FILE.

Jira NVGPU-5353

Change-Id: I67582b68d700b16c46e1cd090f1b938067a364e3
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2336118
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
cd7194cbc0 gpu: nvgpu: modify gmmu page table entry functions 
Move below chip agnostic gmmu pte functions to common/mm/gmmu/pte.c.
- gmmu_aperture_mask()
- pte_dbg_print()

Default big page size for all chips is 64K. So, move
gp10b_mm_get_default_big_page_size() to common file and rename as
nvgpu_gmmu_default_big_page_size().

Modify gv11b_gpu_phys_addr() to use get_iommu_bit() hal.

JIRA NVGPU-4666

Change-Id: I512c42723faf2d03e5b367879c9c385dcf52cdc2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
05df07945a gpu: nvgpu: avoid channel dependency in priv cmdbuf 
The priv cmdbuf queue needs only the vm_gk20a of the channel that owns
it. Pass the vm to the queue constructor and have the channel code store
the queue to itself instead of poking at the channel from the queue
code. Adjust the cmdbuf queue api to take the queue, not the channel.

Move the inflight job fallback calculation to the channel code. The size
of the channel gpfifo isn't needed in the queue; just the job count is.

[not part of the cherry-pick: a bunch of MISRA mitigations.]

Jira NVGPU-4548

Change-Id: I4277dc67bb50380cb157f3aa3c5d57b162a8f0ba
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329659
(cherry picked from commit 83b2276f7bea563602eee20ce24b70ce70c8475a)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332508
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 2020-12-15 14:13:28 -06:00
Konsta Hölttä
991002c88b gpu: nvgpu: hide struct priv_cmd_entry 
The type for entries allocated from the priv cmd queue is no longer
necessary to be visible for its users other than as an opaque handle,
except for a few minor debug prints. Make those prints output the entry
pointer value instead and move the struct definition to priv_cmdbuf.c.

Jira NVGPU-4548

Change-Id: Ia75ff41d840ac928561525a46d5973640e4b5f7e
Signed-off-by: Konsta Hölttä <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2329658
(cherry picked from commit 3292cdadbc78ca129d1e0878c3947b0839487fc2)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2332507
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 2020-12-15 14:13:28 -06:00
Abdul Salam
076c85f813 gpu: nvgpu: Move clk_pmu struct from public include to unit include 
As a part of refactoring move nvgpu_clk_pmupstate from public to
private include.
Also remove all function pointers from the struct and use functions
as only single pstate is supported.
This function pointers were created to address multiple pstate support
which no more needed now.

NVGPU-4690

Change-Id: Iee556feed4a25902faba87a606418861185e4089
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2334826
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 2020-12-15 14:13:28 -06:00
Vedashree Vidwans
6974f784e2 gpu: nvgpu: Update cbc_init_support() return error 
Currently, nvgpu_cbc_init_support() doesn't return error if
cbc.alloc_comptags() fails. Modify nvgpu_cbc_init_support() to check
error returned by cbc.alloc_comptags(). If alloc_comptags() fails, free
allocated cbc memory and set cbc pointer to NULL.

JIRA NVGPU-4666

Change-Id: Id7edaeebc81e7d7029d98bcdbffaf6506c8f0979
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2317822
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 2020-12-15 14:13:28 -06:00
Abdul Salam
88d3640bc5 gpu: nvgpu: Refacotor clk_domain Unit 
As a part of refactoring this patch does the following
*Move local struct to unit specific header file
*Move nvgpu_pmu_clk_domain_freq_to_volt from clk.c to
clk_domain.c
*Move PMU specific struct to ucode_clk_inf.h
*Merge content from nvgpu/clk.h to pmu/clk/clk.h
*Update yaml file
This will help to have arch consistency across all units.

Change-Id: Ied5c6ee637e7fd5bbdee3f5bc3f6cf216454428a
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2333366
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 2020-12-15 14:13:28 -06:00
Divya Singhatwaria
c060e754fc gpu: nvgpu: ELPG dump stats at shutdown 
ELPG_DISALLOW command fails during gk20a shutdown.
It was due to nvgpu_can_busy() which was returning
0 before without acknowledging the ELPG_DISALLOW
command.

Since the system is shutting down so fix this issue
by setting the ACK for disallow command without
waiting for actual ACK from PMU.
In doing so the state machine is also maintained
properly and the driver does not dump fail stats.

BUG 200588696

Change-Id: I943d8e6108fa0f9c418ccb1a7f061307823f1ec6
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
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 2020-12-15 14:13:28 -06:00