There are three issues with shadow domain submission:
1. runlist mem is not being swapped with mem_hw for shadow domain when
there is non-shadow domain being bound to tsg which does not allow runlist
to have all the tsgs. To fix this nvgpu_runlist_swap_mem() is being called
for shadow domain as well.
2. tsg num_active_channels is being set as part of non-shadow domain which
does happen after shadow domain. Due to this, runlist tsg length is not
being set as part of runlist reconstruct and leaving tsg length 0 for last
tsg. To fix this, tsg num_active_channels always get set for shadow domain
as it gets configured first.
3. NV_BUILD_CONFIGURATION_VARIANT_IS_EMBEDDED is not solving the purpose
to differentiate l4t and embedded_linux builds so using
NV_BUILD_SYSTEM_TYPE in place of this to find out the build type.
L4t is using round robin scheduling and this issue coming with manual mode
scheduling so adding the fix only for manual mode scheduling support.
Bug 3884011
Change-Id: Ic55da8f75294eb32c8df6e35fb1fa47df78db8f8
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2833880
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hw register checker detects and error on local setup by nvdvms team.
register readout in GVS and nvdvms team setup is different.
On Finial System, Checker is expected to run after init
But on GVS, Checker runs as a test case along with test other GPU tests.
This lead to mismatch between local and gvs testing.
register missmatch detected by an hw register checker is not really
an error, its related to information.
There are two cases for updating mask value
1. These interrupts are mainly for sw information not any errors
2. These are temporary values ready from board
We will update these values again once we get finial list from HW team
so, we can avoid checking bits 4:7, which represents
* NV_RUNLIST_INTR_0_RUNLIST_IDLE 4U:4U /* RWIVF */
* NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE 5U:5U /* RWXVF */
* NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE 6U:6U /* RWXVF */
* NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE 7U:7U /* RWXVF */
Bug 3912656
Change-Id: I75d1d4737897ef44e78329ed708e86637e8bcf48
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2831273
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This patch introduces the flag NVGPU_DISABLE_STATIC_POWERGATE. Further,
static pg related initialization APIs have been updated to check whether
this newly added flag is enabled. If this flag is enabled, then static
pg init gets skipped.
JIRA NVGPU-9350
Change-Id: I450b6dd2c541d31fc40fb5540e557b5db730fee2
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2834021
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gv11b onwards add hals
get_hwpm_gpcrouter_perfmon_regs_base
get_hwpm_fbprouter_perfmon_regs_base
And remove the ga10b version of same as that is redundant.
This is preparatory patch to update the gr_gv11b_pri_pmmgpcrouter_addr
and gr_gv11b_pri_pmmfbprouter_addr with the hals
JIRA NVGPU-9073
Change-Id: I8b04f9b61784ca2c09b248655435ea7a7ab92926
Signed-off-by: Ramalingam C <ramalingamc@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2828584
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ankur Kishore <ankkishore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This change is to adapt to shift of ACR t234 safety code from
iGPU to dGPU.
Required changes consists of:
Adding support for new LSB, WPR and ACR descriptor structures
which are more aligned with what dGPU currently uses.
Change old riscv LSB header to version 1, as version 2 will
be used for new header to align with dGPU header nomenclature.
Jira NVGPU-9298
Change-Id: Id75f7d0a03dc65c1983822ead428b330a83481a1
Signed-off-by: mpoojary <mpoojary@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2811116
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Currently the gsp scheudler is enabled for all linux configurations and
this change will enable the gsp scheduler on embedded linux profile and
will disable on l4t.
One of the gsp ga10b hal funcion is used by nvgpu-next so the defination
is moved out of gsp scheduler flag
NVGPU-9297
Change-Id: If457db46e26d8f5be01f643c75a22aafb86bd7f3
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2826152
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The patch is adding a OS specific call to get the supported
syncpoints from the DT entry. The syncpoints is used to
initialize the number of supported channels while GPU
initialization.
The error path is taken care with the default value 256.
As device tree entries not available in upstream, the path
handled with the default value 256.
Change-Id: I9ac949d68a9f93f0e56fdbf8c8cd33b7dc903298
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2826280
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Arto Merilainen <amerilainen@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
EPL lib constructor is replaced by NvEplInit() by safety services.
NvGPU, being an EPL user, needs to call NvEplInit before using EPL
API to report errors.
NvEplInit() usage is limited to user space in Linux, so NvGPU is not
expected to call NvEplInit on Linux.
Bug 3863536
Change-Id: I7fc9b33d3443bd39a6367a0c691bddb80b9edb68
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2817245
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The memory leak issue was due to nvgpu_profiler_unbind_context() calling
nvgpu_profiler_pm_resource_release() for all resources which clears the
flag required by nvgpu_profiler_free_pma_stream() to release the memory
for perf_buf instance block.
Fixing this issue by splitting nvgpu_profiler_unbind_context() to release
all the pm resources at a later time separately.
Bug 3510455
Change-Id: Ibab8d071693e600c46f7e7f16575e36e6f62af3c
Signed-off-by: atanand <atanand@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2825013
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Dinesh T <dt@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This patch is required for
- enabling NVGPU driver on OOT by enabling various
configs required.
- replacing new APIs for some deprecated APIs by
guarding with linux version for soc.c.
- CONFIG_TEGRA_HV_MANAGER is enabled by default in OOT kernel,
removing CONFIG_TEGRA_HV_MANAGER check from various places.
Bug 3812973
Change-Id: I07f0b738ca95d4a3996e7f3ee5e895463db0626b
Signed-off-by: Dinesh T <dt@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822434
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On T234 theCTXSW LS ucodes are encrypted. ACR will perform the
decryption and the decrypted content will be written back
into the same WPR location. So on recovery with LSPMU absence
and on warm boot case, to perform the authentication , the ucode
blob needs to be copied into the WPR from sysmem always.
Below are the LS ucodes authentication type
* LSPMU - Only Signed ( Only for non-safety build, for safety LSPMU is NA)
* CTXSW FECS/GPCCS - Encrypted and Signed (on both safety and non-safety build)
ACR FW P4 Change : 32110924
JIRA NVGPU-7903
Change-Id: If447148c02b9cf310102cfb9c688eef402699409
Signed-off-by: Dinesh Kamalakannan <dineshka@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822656
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Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
For ASIL-D decomposision we need hw register checker to validate
potential register configurations done at init phase
This is the tool used to generate hw registers table that needs to be
validated on the target.
* Generate register list
- register addresses are picked from hw headers
- register value masks are hardcoded for validation
Jira NVGPU-8885
Change-Id: I875735b6ae6b5e94eb85e67ca802a23b7d250598
Signed-off-by: Sagar Kadamati <skadamati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2823929
Reviewed-by: Alex Waterman <alexw@nvidia.com>
nvpmodel updates the devfreq frequency limits as per power requirements
for specific chip. Clock arbiter ignored these limits and set clock
to maximum supported frequency which may lead to leaking power and
over heating.
Add support to get the devfreq limits by registering PM_QOS notifiers.
Note that with this patch we enable CONFIG_GK20A_PM_QOS when PM_DEVFREQ
is enabled. So it will be enabled for all supported kernels (4.9, 4.14
kernels continue to support this. For 5.10+ kernels notifiers added in
this patch will be used. Thermal framework related notifiers for kernels
after 4.14 will not be registered as those use downstream interfaces
that are not available.)
We maintain devfreq min/max limits in the scale profile and update those
in the notifier calls. We use these limits to clamp the frequency in the
clock arbiter.
Bug 3852824
Change-Id: I734a9fb080fee1a91e9b5da071b662dbd9a18682
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822686
(cherry picked from commit eacaf8cec2)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822682
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Changes
1. Remove dGPU flag dependency on calling gsp sw init on tot.
2. Created Enable flag for gsp scheduler to enable them on ga10b
platforms.
3. Engine config flag is only enabled for dGPU enabled platforms, as gsp
is using engine functions it need to be enabled for all gsp sched
enabled builds.
4. Changes in gsp_sequence_init/de_init where on qnx we are seeing
issues.
NVGPU-9297
Change-Id: Ia4bce85ae8fd2794da1553e9ea418c76845a10ac
Signed-off-by: rmylavarapu <rmylavarapu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2822537
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HSI Error injection utility on QNX is compiled only when
NV_BUILD_CONFIGURATION_IS_DEBUG or NV_BUILD_CONFIGURATION_IS_VLTEST
build options are enabled. Remove the NvGPU error injection support
dependency on CONFIG_TEGRA_HSIERRRPTINJ as it is used only on Linux.
Also, the safety build support will be moved to Mon, so enable
CONFIG_NVGPU_FSI_ERR_INJECTION only on regular build.
JIRA NVGPU-7440
Change-Id: Ibbdd0aabfa7c5a4f3aee51cdf6bdadbb814bdfeb
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2820579
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
- As part of mmap call handler mmap_sem is being acquired which is
causing an BUG: scheduling while atomic:. This is happening because
mmap callback gets called with mmap_sem held. The mmap file handler
is called via call_mmap() via mmap_region() via do_mmap(), and the
caller of do_mmap() must hold down_write(¤t->mm->mmap_sem).
To fix this issue removing the mmap_sem locking from nvs mmap handler.
- If remap_vmalloc_range() is used to map the pages to userspace then
allocated pages should be mapped into virtually contiguous space by
passing VM_USERMAP flag to vmap(). Passing VM_USERMAP to vmap() call
if API nvgpu_dma_alloc_flags_sys() is called with flag
NVGPU_DMA_VM_USERMAP_ADDRESS.
Bug 3884011
Change-Id: I64264f6f6e0dd75b1f828dc58355d740e6ef5ccb
Signed-off-by: prsethi <prsethi@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2820781
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