Reduce code complexity of following functions in common.gr.intr
nvgpu_gr_intr_stall_isr(complexity : 33)
nvgpu_gr_intr_handle_sm_exception(complexity : 17)
Create sub functions by moving the control statement codes from the
function which has high complexity above 10.
Create five sub functions from nvgpu_gr_intr_stall_isr function.
Four of the sub functions based interrupt types.
One sub function for getting the channel information from context
gr_intr_get_channel_from_ctx(complexity : 4)
gr_intr_handle_exception_interrupts(complexity : 11)
This function complexity will reduce with NVGPU_DEBUGGER disable
gr_intr_handle_illegal_interrupts(complexity : 5)
gr_intr_handle_error_interrupts(complexity : 7)
gr_intr_handle_pending_interrupts(complexity : 3)
and reduce nvgpu_gr_intr_stall_isr complexity to 9
Create one sub functions from nvgpu_gr_intr_handle_sm_exception function
One sub function to report back any warp error.
gr_intr_report_warp_error(with complexity : 3)
and reduce nvgpu_gr_intr_handle_sm_exception complexity to 15
This function complexity will reduce with NVGPU_DEBUGGER disable
Jira NVGPU-3662
Change-Id: Ib325d9d8bca6b48766bc8a75f428dceeac495850
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2160578
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This patch adds the support to handle and report graphics related
exceptions to 3LSS. Specifically, it adds the following exceptions:
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_CROP
NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_ZROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PROP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_ZCULL
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_SETUP
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES0
NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_PES1
NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_PE
JIRA NVGPU-3457
Change-Id: Ib24b67ed33ae139317ec85bba3fbb80ba51fd384
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2158609
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Trap handling and SM preprocessing is not needed in safety build i.e.
when NVGPU_DEBUGGER is false
Add NVGPU_DEBUGGER flag for all unsafe processing.
In safety build we only report the SM exceptions and return error
so that recovery is triggered
Also add flag for gr_intr_post_bpt_events() since event handling
is not needed in safety build
Jira NVGPU-3506
Change-Id: I660930fdb185b82c0adb612decbfd3d014ce2524
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127754
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Move some interrupt handling hals from hal.gr.gr unit to hal.gr.intr
unit as below
g->ops.gr.intr.set_hww_esr_report_mask()
g->ops.gr.intr.handle_tpc_sm_ecc_exception()
g->ops.gr.intr.get_esr_sm_sel()
g->ops.gr.intr.clear_sm_hww()
g->ops.gr.intr.handle_ssync_hww()
g->ops.gr.intr.log_mme_exception()
g->ops.gr.intr.record_sm_error_state()
g->ops.gr.intr.get_sm_hww_global_esr()
g->ops.gr.intr.get_sm_hww_warp_esr()
g->ops.gr.intr.get_sm_no_lock_down_hww_global_esr_mask()
g->ops.gr.intr.get_sm_hww_warp_esr_pc()
g->ops.gr.intr.tpc_enabled_exceptions()
g->ops.gr.intr.get_ctxsw_checksum_mismatch_mailbox_val()
Rename gv11b_gr_sm_offset() to nvgpu_gr_sm_offset() and move to
common.gr.gr unit
All of above functions and hals will be needed in safety build
Jira NVGPU-3506
Change-Id: I278d528e4b6176b62ff44eb39ef18ef28d37c401
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2127753
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
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This flag is added to compile out below features from
safety build
-set_preemption_mode
-channel_enable
-channel_disable
-channel_preempt
-channel_force_reset
-tsg_enable
-tsg_disable
-tsg_preempt
-tsg_event_id_ctrl
-post_event_id
JIRA NVGPU-3516
Change-Id: I935841db766f192f62598240c0e245a2959555be
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2126829
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This patch moves gops init related to SDL from qnx to common-core. For this
purpose, it does the following changes:
- Adds stub functions for linux and posix.
- Updates nvgpu_init.c for mapping err_ops with report error APIs.
- Updates nvgpu_err.h header file to include prototypes related to error
reporting APIs.
- Updates nvgpu-linux.yaml file to include sdl_stub file.
Jira NVGPU-3237
Change-Id: Idbdbe6f8437bf53504b29dc2d50214484ad18d6f
Signed-off-by: Rajesh Devaraj <rdevaraj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119681
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channel.c calling nvgpu_gr_flush_channel_tlb() creating circular
dependency between gr and fifo. Avoid this by moving channel tlb
related data to struct nvgpu_gr_intr in gr_intr_priv.h and
initialized this data in gr_intr.c.
Created following new gr intr hal and called this new hal from channel.c
void (*flush_channel_tlb)(struct gk20a *g);
JIRA NVGPU-3214
Change-Id: I2d259bf52db967273030680f50065af94a17f417
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109274
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Separate out cyclestats handling code into separate unit
common.cyclestats
This unit now exposes new API nvgpu_cyclestats_exec() to perform
cyclestats operation. Call this API from common.gr.intr unit
Extract out all the private data structures from gk20a.h to
cyclestats_priv.h
Rename struct gk20a_cyclestate_buffer_elem to
nvgpu_cyclestate_buffer_elem
Jira NVGPU-1103
Change-Id: Id362675228fe23d03d6d277ff320bcc1066c3c64
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2104202
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
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Move gr_gk20a_handle_fecs_error from gr_gk20a.c to
nvgpu_gr_intr_handle_fecs_error in common.gr.intr unit
Move gr_gp10b_handle_fecs_error and gr_gv11b_handle_fecs_error
to hal.gr.intr unit
JIRA NVGPU-3016
Change-Id: I5b7c48ebfd7b13f497980c4d0b64d718649154bd
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103741
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Move gr_gp10b_handle_sm_exception from gr_gp10b to
gp10b_gr_intr_handle_sm_exception in hal.gr.intr unit
Move gr_gk20a_handle_sm_exception from gr_gk20a to
nvgpu_gr_intr_handle_sm_exception in common.gr.intr
Move nvgpu_report_gr_sm_exception to common.gr.intr
JIRA NVGPU-3016
Change-Id: I545ddca052122f87685f35f515831841a246dab3
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103736
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Removed unused struct from gr_gk20a.h
Change static allocation for struct gr_gk20a to dynamic type.
Change all the files that being affected by that change.
Call gr allocation from corresponding init_support functions, which
are part of the probe functions.
nvgpu_pci_init_support in pci.c
vgpu_init_support in vgpu_linux.c
gk20a_init_support in module.c
Call gr free before the gk20a free call in nvgpu_free_gk20a.
Rename struct gr_gk20a to struct nvgpu_gr
JIRA NVGPU-3132
Change-Id: Ief5e664521f141c7378c4044ed0df5f03ba06fca
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2095798
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Move the nvgpu_report_gr_exception call from gr_gk20a to
gr_intr.c as nvgpu_gr_intr_report_exception
Move local function gk20a_gr_get_channel_from_ctx to gr_intr.c
as nvgpu_gr_intr_get_channel_from_ctx
JIRA NVGPU-1891
Change-Id: I21521ad50989582d8f166a98a21ea3b1dcd3bbff
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2098229
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Move the gk20a_gr_handle_gpc_exception function from gr_gk20a.c
to gr_intr.c as nvpu_gr_intr_handle_gpc_exception.
Move static function gk20a_gr_handle_tpc_exception to
gr_intr.c as gr_intr_handle_tpc_exception
JIRA NVGPU-3016
Change-Id: I42862b00d1946e029673d8f95e0262a44244a87a
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090405
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Move handle_semaphore_pending to hal.gr.intr
gr_gk20a_handle_semaphore_pending function is moved from
gr_gk20a.c to common.gr.intr as nvgpu_gr_handle_semaphore_pending
JIRA NVGPU-3016
JIRA NVGPU-1891
Change-Id: Id731bb4169de9dcfff012e401165ad5a7f43bffa
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089173
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Move handle_notify_pending hal to hal.gr.intr
Move gk20a_gr_handle_notify_pending code from gr_gk20a.c to
common.gr.intr as nvgpu_gr_intr_handle_notify_pending function.
JIRA NVGPU-1891
JIRA NVGPU-3016
Change-Id: Ib3284a83253b03e5708674fce683331ee20b8213
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2089172
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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