Commit Graph

46 Commits

Author SHA1 Message Date
Richard Zhao
c3b5b48c0f gpu: nvgpu: move slices_per_ltc & cacheline_size init to floorsweeping
It was initialized at .init_comptags, but we may also need them without
comptags.

Jira NVGPUT-63

Change-Id: Ie818c3ecf890fc84323b9662a32d666a6d2b3936
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1756373
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2018-06-21 13:58:07 -07:00
Terje Bergstrom
dd739fcb03 gpu: nvgpu: Remove gk20a_dbg* functions
Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.

Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.

Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
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2018-05-09 18:26:04 -07:00
Richard Zhao
687b1059f0 gpu: nvgpu: save max_comptag_lines in gr
max_comptag_lines will be used by RM server to calculate how many lines
each guest can get.

Jira VQRM-2345

Change-Id: If52208d79617f2f894e48d3a4daec186fda862f1
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1695082
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2018-04-25 09:36:11 -07:00
Terje Bergstrom
e7cc24eb9b gpu: nvgpu: Correct sign qualifiers for LTC code
In constants we use in LTC code we miss the qualifier indicating
if the constant is signed or unsigned. Add qualifiers for LTC code
and the ZBC related constant used in LTC code.

Change-Id: Id80078722f8a4f50eb53370146437bebb72a3ffc
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1683859
Reviewed-by: Alex Waterman <alexw@nvidia.com>
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2018-04-03 17:05:19 -07:00
Terje Bergstrom
cb9f8bae1a gpu: nvgpu: Unify querying stream id
Stream ID for gp10b is retrieved directly from DT headers in common
code. Introduce instead a variable to store the stream ID and move the
query to platform_gp10b_tegra.c.

JIRA NVGPU-4

Change-Id: I123024e13e470283bb691883f8f963eb72c997d8
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1648013
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2018-01-31 12:37:28 -08:00
Terje Bergstrom
fb0a23ea16 gpu: nvgpu: Implement gp10b variant of cbc_ctrl
Pascal has support for more comptags than Maxwell, but we were using
gm20b definitions for cbc_ctrl on all chips. Specifically field
clear_upper_bound is one bit wider in Pascal.

Implement gp10b version of cbc_ctrl and take that into use in Pascal
and Volta.

Bug 200381317

Change-Id: I7d3cb9e92498e08f8704f156e2afb34404ce587e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642574
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2018-01-24 14:42:16 -08:00
Deepak Nibade
3e9aa581b6 gpu: nvgpu: skip comptag re-initialization
In case we need to re-initialize GR after floorsweeping TPC,
gp10b_ltc_init_comptags() will try to allocate comptag memory again

Skip this during re-initialization since it is unnecessary to
re-allocate all those buffers

Comptag buffer size is 33MB and reallocating causes huge memory leak
anyways

Bug 2031635

Change-Id: I935f96eb133283d6f935589c0e581e0997e980e2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1634737
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
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2018-01-10 05:16:44 -08:00
David Nieto
8fb6a8562e gpu: nvgpu: gv11b: Report LTC errors per slice
Add support to report ltc ecc errors per slice

(1) use new logic to detect subunits
(2) store size of array and check before comparison to prevent out of bounds
 derefencing
(3) use new hashing to prevent collisions or entries with permuted names

bug 2037425

Change-Id: I63b9f0df43b9dceddc1bae17924c4723072f569e
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1620854
GVS: Gerrit_Virtual_Submit
Reviewed-by: Chris Dragan <kdragan@nvidia.com>
Tested-by: Chris Dragan <kdragan@nvidia.com>
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
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2017-12-28 10:01:36 -08:00
Terje Bergstrom
9d04e97093 gpu: nvgpu: Remove separation of t18x code
Remove separation of t18x specific code and fields and the associated
ifdefs. We can build T18x code in always.

Change-Id: I4e8eae9c30335632a2da48b418c6138193831b4f
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595431
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2017-11-17 16:29:41 -08:00
Alex Waterman
016231c045 gpu: nvgpu: Use only contig CBCs
Modify the LTC code to only use a contiguous CompBit Cache (CBC). The
original code had two allocation schemes: "physical" and "virtual" -
what they meant was virtually contiguous or physically contiguous. The
CBC must appear contiguous to the GPU be it either from the IOMMU or
from physical pages allocated contiguously.

This change makes the CBC get allocated with the FORCE_CONTIGUOUS flag
if the GPU is not IOMMU'able. If we can get contiguous mem with the
IOMMU then no need to force the underlying pages to be contiguous.
However, not all GPUs may be IOMMU'able so we do need to handle that
case.

Also delete the gk20a/ltc_gk20a.[ch] code. All that remained in these
files was the CBC alloc functions which were completely chip agnostic.
As a result these functions were consolidated and moved to common/ltc.c.

Bug 2015747

Change-Id: I3f41961b4f94378b954e7502a6b27cf0bc627375
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1593666
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
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2017-11-08 17:11:30 -08:00
Alex Waterman
b3446bc0b6 gpu: nvgpu: Move dma_buf usage from mm_gk20a.c
Move most of the dma_buf usage present in the mm_gk20a.c code
out to Linux specific code and some commom/mm code. There's
two primary groups of code:

  1. dma_buf priv field code (for holding comptag data)
  2. Comptag usage that relies on dma_buf pointers

For (1) the dma_buf code was simply moved to common/linux/dmabuf.c
since most of this code is clearly Linux specific.

The comptag code was a bit more complicated since there is two
parts to the comptag code. Firstly there's the code that manages
the comptag memory. This is essentially a simple allocator. This
was moved to common/mm/comptags.c since it can be shared across
all chips. The second set of code is moved to
common/linux/comptags.c since it is the interface between dma_bufs
and the comptag memory.

Two other fixes were done as well:

 - Add struct gk20a to the comptag allocator init so that
   the proper nvgpu_vzalloc() function could be used.
 - Add necessary includes to common/linux/vm_priv.h.

JIRA NVGPU-30
JIRA NVGPU-138

Change-Id: I96c57f2763e5ebe18a2f2ee4b33e0e1a2597848c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1566628
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2017-10-18 16:00:37 -07:00
Terje Bergstrom
7885500a42 gpu: nvgpu: Change license for common files to MIT
Change license of OS independent source code files to MIT.

JIRA NVGPU-218

Change-Id: I1474065f4b552112786974a16cdf076c5179540e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1565880
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2017-09-26 11:37:32 -07:00
Terje Bergstrom
b8efd9d045 gpu: nvgpu: Make LTC disabling common code
Refactor the sync_debugfs LTC HAL op so that the logic to enable
or disable LTC goes to common code nvgpu_ltc_sync_enabled() and
the LTC HAL set_enabled only performs the hardware register access.

Create a new common function nvgpu_init_ltc_support() to initialize
the LTC software variable, and move hardware initialization of LTC to
be called from it.

JIRA NVGPU-62

Change-Id: Ib1cf4f5b83ca3dac08407464ed56a732e0a33923
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1528262
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2017-08-04 09:23:56 -07:00
Sunny He
0dc80244ee gpu: nvgpu: Reorganize ltc HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the ltc
sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I1110e301e57b502cf7f97e6739424cb33cc52a69
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1507564
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2017-06-27 10:44:11 -07:00
Sunny He
773df3f5e9 gpu: nvgpu: remove ltc_common.c
Remove ltc_common.c and integrate the included functions
into device specific ltc_gXXXX.c files. Merge non-device reg
definition dependent ltc functions into ltc_gk20a.c/h.

Prior to this patch, ltc_common.c was being directly included
into the device specific ltc source files as a workaround to
allow different devices to share the same code but still include
in different hw reg definitions.

Given that this approach was not adopted for other
systems, this code has been separated out for readability and
consistency.

Jira NVGPU-74

Change-Id: I4eea301927418532cc150b029535f165928cab89
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master/r/1507502
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-06-27 10:44:05 -07:00
David Nieto
651f970d1c gpu: nvgpu: chip specific L2 ECC error support
Adding support for handling of chip specific ECC memory errors

JIRA: GPUT19X-112

Change-Id: I1c04ac1d5233c332b300540eade1b73527c46ff7
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1489020
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-06-04 20:34:57 -07:00
Alex Waterman
66a2511a36 gpu: nvgpu: Begin removing variables in struct gk20a
Begin removing all of the myriad flag variables in struct gk20a and
replace that with one API that checks for flags being enabled or
disabled. The API is as follows:

  bool nvgpu_is_enabled(struct gk20a *g, int flag);
  bool __nvgpu_set_enabled(struct gk20a *g, int flag, bool state);

These APIs allow many of the gk20a flags to be replaced by defines.
This makes flag usage consistent and saves a small amount of memory in
struct gk20a. Also it makes struct gk20a easier to read since there's
less clutter scattered through out.

JIRA NVGPU-84

Change-Id: I6525cecbe97c4e8379e5f53e29ef0b4dbd1a7fc2
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1488049
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2017-05-30 13:24:35 -07:00
David Nieto
05388ad24a gpu: nvgpu: re-arrange parity counters
(1) Re-arrange the structure for parity counters reporting so multiple
units can be managed

JIRA: GPUT19X-84

Change-Id: If59a883dfe22d5a1d91a6d0ed2f5a6254434ffcb
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1485276
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-05-24 04:55:59 -07:00
Sachin Nikam
4f0436de19 nvgpu: fix static sparse warnings
Fixed below static sparse warnings by making either
function as static or including right header.

- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/common/linux/module.c:816:5: warning: symbol 'gk20a_pm_init' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/bus_gk20a.c:28:6: warning: symbol 'gk20a_bus_init_hw' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/bus_gk20a.c:54:6: warning: symbol 'gk20a_bus_isr' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/bus_gk20a.c:90:5: warning: symbol 'gk20a_read_ptimer' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/bus_gk20a.c:147:6: warning: symbol 'gk20a_init_bus' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c:232:6: warning: symbol 'gk20a_init_ltc' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gk20a/fb_gk20a.c:75:6: warning: symbol 'gk20a_fb_debug_mode_enabled' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/hal_gm20b.c:184:5: warning: symbol 'gm20b_init_hal' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/fb_gm20b.c:165:5: warning: symbol 'gm20b_fb_vpr_info_fetch' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:103:5: warning: symbol 'gm20b_ltc_cbc_ctrl' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:168:6: warning: symbol 'gm20b_ltc_init_fs_state' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:195:6: warning: symbol 'gm20b_ltc_isr' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:221:5: warning: symbol 'gm20b_ltc_cbc_fix_config' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:236:6: warning: symbol 'gm20b_flush_ltc' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c:350:6: warning: symbol 'gm20b_init_ltc' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/tegra/linux/clk.c:72:6: warning: symbol 'nvgpu_linux_init_clk_support' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c:206:6: warning: symbol 'gp10b_init_ltc' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/fb_gp10b.c:98:6: warning: symbol 'gp10b_init_fb' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/hal_gp10b.c:190:5: warning: symbol 'gp10b_init_hal' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp10b/priv_ring_gp10b.c:79:6: warning: symbol 'gp10b_init_priv_ring' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp106/hal_gp106.c:222:5: warning: symbol 'gp106_init_hal' was not declared. Should it be static?
- $TOP/kernel/nvgpu/drivers/gpu/nvgpu/gp106/fb_gp106.c:42:6: warning: symbol 'gp106_init_fb' was not declared. Should it be static?

Bug 200299572

Change-Id: I32f9a3cb65314bd1eb1a6d93cda5796cfa64d738
Signed-off-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-on: http://git-master/r/1481804
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-05-16 02:32:35 -07:00
Terje Bergstrom
6df49a63ca gpu: nvgpu: Move is_fmodel to struct gk20a
Copy is_fmodel to struct gk20a at probe time, and access it from
gk20a instead of platform_gk20a.

JIRA NVGPU-16

Change-Id: Ib8d793ea2b02b62da3bfdbb6372d9927658b7ec6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1463540
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-04-19 13:24:30 -07:00
Terje Bergstrom
57d624f900 gpu: nvgpu: gp10b: Use new error macros
gk20a_err() and gk20a_warn() require a struct device pointer,
which is not portable across operating systems. The new nvgpu_err()
and nvgpu_warn() macros take struct gk20a pointer. Convert code
to use the more portable macros.

JIRA NVGPU-16

Change-Id: I8dc0ddf3b6ea38af6300c27558b60786c163da6d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1457344
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-04-10 19:04:20 -07:00
Terje Bergstrom
f116320137 gpu: nvgpu: Add wrapper for linux/types.h
Add wrapper header nvgpu/types.h. It checks if build is for Linux
kernel and pulls in linux/types.h.

Delete also all #includes for linux/types.h which are not strictly
necessary, and change the remaining ones to use the new wrapper.

JIRA NVGPU-13

Change-Id: I1ddfef0b0b9d840e3e41a62f69c7cb9148d2d5fa
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1453371
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2017-04-03 14:04:10 -07:00
Terje Bergstrom
866fee0247 gpu: nvgpu: Remove ELPG_FLUSH
ELPG_FLUSH is not accessible in later GPUs, so we stopped using it
and instead do explicit CBC and L2 flushes. Delete the unused
function op and backing code.

Change-Id: Ic3eb97f2d32ea8fdbe5ec57bd9254268caaf9935
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1323236
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
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2017-03-20 16:40:02 -07:00
Alex Waterman
865514be2d gpu: nvgpu: Move gp10b HW headers
Move the gp10b HW headers to a new directory specially for them:

  include/nvgpu/hw/gp10b

And change the code to include like so:

  #include <nvgpu/hw/gp10b/hw_fb_gp10b.h>

This is part of the process to restructure the nvgpu driver.

Bug 1799159

Change-Id: Ic80ea5b7f5c280839e502e2178a345181f7a7ef9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1280326
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-01-11 12:44:14 -08:00
Terje Bergstrom
d8da1d6438 gpu: nvgpu: Fix signed comparison bugs
Fix small problems related to signed versus unsigned comparisons
throughout the driver. Bump up the warning level to prevent
such problems from occuring in future.

Change-Id: Ib7026728ef0e8c3c9e68956fc9794ec3a786a8a2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252069
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2016-12-27 15:26:51 +05:30
Seema Khowala
436109f46d gpu: nvgpu: gp10b: add is_fmodel check
Check for is_fmodel instead of check
for simualtion platforms.

Bug 1735760

Change-Id: I14e349088e9414a73353a94613fa031e63bfa31f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1177200
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-by: Ayoosh Bansal <ayooshb@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
2016-12-27 15:26:18 +05:30
Terje Bergstrom
205559cf31 gpu: nvgpu: Remove setting op set_max_ways_evict_last
Do not set op set_max_ways_evict_last. It gets removed from
ltc_gk20a.c, and it's never called in gm20b and beyond anyway.

Change-Id: Ib8851057810aa8ddf2088c9e9245e4caf469bddf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1146882
2016-12-27 15:26:15 +05:30
Terje Bergstrom
342d45e060 gpu: nvgpu: gp10b: Add litter values HAL
Move per-chip constants to be returned by a chip specific function.
Implement get_litter_value() for each chip.

Change-Id: I8bda9bf99b2cc6aba0fb88a69cc374e0a6abab6b
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1121384
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
2016-12-27 15:22:12 +05:30
Adeel Raza
e9b03e903c gpu: nvgpu: gp10b: add ECC stats sysfs nodes
Add sysfs nodes for querying ECC single/double bit error counts.

Bug 1699676

Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935363
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:22:10 +05:30
Adeel Raza
f17e0d822b gpu: nvgpu: gp10b: add ECC support
Add ECC exception handling support for SM, TEX, and LTC.

Bug 1635727
Bug 1637486

Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935362
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
2016-12-27 15:22:10 +05:30
Konsta Holtta
1ec6d2b6d6 gpu: nvgpu: bitmap allocator for comptags
Restore comptags to be bitmap-allocated, like they were before we had
the buddy allocator.

Bug 200145635

Change-Id: I681493871096f437014b7eca1182fefbaf7f6a74
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/839240
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:22:10 +05:30
Alex Waterman
528c08b501 arm64: tegra: dts: Use new SID dt-bindings
Use bindings more specific to the ARM SMMU.

Change-Id: I0e2df8e8e7bfa51036a84e923fa06e42bbed3cd7
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/812438
(cherry picked from commit 98cb259c87e9531b0a21dfd3132a3f3db07ff6f0)
Reviewed-on: http://git-master/r/831515
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Tested-by: Krishna Reddy <vdumpa@nvidia.com>
2016-12-27 15:22:09 +05:30
Terje Bergstrom
6b4a7ed432 gpu: nvgpu: gp10b: Rewrite compbit backing store calc
Compbit backing store did not take into account number of GOBS
per comptagline per slice.

Bug 1604102

Change-Id: I42666e72ea54697b6fbc7318e65a6a09d867f5b6
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/754706
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sami Kiminki <skiminki@nvidia.com>
2016-12-27 15:22:06 +05:30
Bharat Nihalani
dfe6493dcb Revert "gpu: nvgpu: fix allocator_init() calls"
This reverts commit 053037f1450d6ba6c5d01abcdcd9b24019ae8c85
since the issue seen with bug 200106514 is fixed with change
http://git-master/r/#/c/752080/.

Bug 200112195

Change-Id: If54eb570fd2ad5de99d180d03d5d90492283fe33
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/752504
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:22:06 +05:30
Deepak Nibade
021748b782 gpu: nvgpu: fix allocator_init() calls
Change for new VA space allocator is being reverted with
http://git-master/r/#/c/749291/ but only for Kernel3.18

In Kernel3.10, we support the new VA allocator

Since we support both the kernel versions as of now,
use a KERNEL_VERSION based mechanism to select
appropriate call

Define new macro NVGPU_USE_NEW_ALLOCATOR for Kernel3.10
where we want to use new allocator

Bug 200106514

Change-Id: I9af26d555278c40e03fe82b0912961a862c8bf55
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/751353
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
2016-12-27 15:22:06 +05:30
Alex Waterman
2907e24e8b Revert "Revert "gpu: nvgpu: gp10b part of new VA allocator""
This reverts commit 30e5947fa1f26ed6bb4f137fd76c8869e91b9829.

The original commit was actually fine.

Signed-off-by: Alex Waterman <alexw@nvidia.com>
Change-Id: I0454415981d29ed0b877f7a21db6f54bc4c30470
Reviewed-on: http://git-master/r/743302
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:22:05 +05:30
Terje Bergstrom
5e18ae63db Revert "gpu: nvgpu: gp10b part of new VA allocator"
This reverts commit 3a4f0285c7e9212b394b2c1b151987a7084de927.

Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Change-Id: I886e434ce98e85f99b0a77749179e31c0bd00620
Reviewed-on: http://git-master/r/741468
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Tested-by: Hiroshi Doyu <hdoyu@nvidia.com>
2016-12-27 15:22:05 +05:30
Alex Waterman
74bdb40327 gpu: nvgpu: gp10b part of new VA allocator
The comptag allocator is made in the chip-specific init code
for the comptags. Thus, a t18x change needs to be made to make
sure the new allocator code compiles and works on t18x.

Change-Id: I57a34f3c61ebd31f875caa577378e829812f2d4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/721171
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:22:05 +05:30
Deepak Nibade
0158c38037 gpu: nvgpu: gp10b: fix sparse warnings of static symbol
Fix sparse warnings of below type by making necessary
symbols static:

warning: symbol '<symbol>' was not declared. Should it be static?

Bug 200088648

Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/728012
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
2016-12-27 15:22:05 +05:30
Terje Bergstrom
4de370c12e gpu: nvgpu: gp10b: Program stream id to LTC
Program a constant stream id 31 to LTC.

Bug 1610019

Change-Id: I9b5fb794b5ea8da0fba67a2376126d89e056f955
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/724348
Reviewed-by: Automatic_Commit_Validation_User
2016-12-27 15:22:04 +05:30
Terje Bergstrom
e3dcb7546a gpu: nvgpu: gp10b: Do not clear compbit store size
Do not clear compbit store size if max size is zero. It's already
zero at this point.

Change-Id: I70d99cfe459fae27d8c1be4aa569ac0717a454d7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/720599
2016-12-27 15:22:04 +05:30
Terje Bergstrom
fc898d8f56 gpu: nvgpu: gp10b specific LTC ISR
LTC interrupt register got moved, so use the new offset.

Bug 1587638

Change-Id: I3dbd44d92f2bcb3634c21ed46870ec1620d936cf
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/709571
Reviewed-by: Automatic_Commit_Validation_User
2016-12-27 15:22:04 +05:30
Jussi Rasanen
99d41c05f5 gpu: nvgpu: read gobs_per_comptagline_per_slice
Add code to read NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE
during t18x ltc init and store it for use in CDE code.

Change-Id: I4d4a3a6c7e3ad369d8359ff838e7040a0521b441
Signed-off-by: Jussi Rasanen <jrasanen@nvidia.com>
Reviewed-on: http://git-master/r/673150
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-12-27 15:22:03 +05:30
Terje Bergstrom
c0fcbdf2fc gpu: nvgpu: gp10b: Compression page size to 64k
Define compression page size for gp10b to be 64k. We also need to
copy some LTC initialization code from gm20b to gp10b.

Change-Id: I0235c32cdb1486a23d33eb98ebbc79c97a3c32d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/677837
2016-12-27 15:22:03 +05:30
Terje Bergstrom
d6ef9c6578 gpu: nvgpu: gp10b: Fix L2 size calculation
L2 size is expressed in kB, so add a multiplier.

Bug 1592495

Change-Id: I4c10034cd21bf874c84c96f1adc25261b195063d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/671704
2016-12-27 15:22:03 +05:30
Terje Bergstrom
7918de1c1b gpu: nvgpu: gp10b: Implement L2 query
Bug 1567274

Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/602858
Reviewed-by: Automatic_Commit_Validation_User
2016-12-27 15:22:02 +05:30