Commit Graph

8 Commits

Author SHA1 Message Date
Terje Bergstrom
27694ca572 gpu: nvgpu: Implement bus HAL for bar2 bind
Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL.
BAR2 bind HW API is in bus.

JIRA NVGPU-588

Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730896
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-06-14 06:44:07 -07:00
Alex Waterman
0f291f0d58 gpu: nvgpu: Remove fault_buf_status array
Now that we have a consistent way to check if a mem allocation
is valid this array is not necessary. The code can simply check
the validity of the nvgpu_mem.

Change-Id: I6aaf563ddc314cf86a2c2b98f7eb75fa7a9a1ad9
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1641637
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2018-01-24 14:41:28 -08:00
Terje Bergstrom
d61643c020 gpu: nvgpu: gv11b: Change license for common files to MIT
Change license of OS independent source code files to MIT.

JIRA NVGPU-218

Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1567804
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: David Martinez Nieto <dmartineznie@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-09-25 17:03:31 -07:00
Sunny He
8ab6445df5 gpu: nvgpu: Reorg mm HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I5fd295c6473d5b4a6178c0c6be8fcf8f4c33f2e3
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537754
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2017-08-14 15:55:25 -07:00
Sunny He
a4e095aa37 Revert "gpu: nvgpu: gv11b: Reorg mm HAL init"
This reverts commit 96615351ad, which
conflicts with gv100 changes.

Change-Id: I08797bb23dd9226f0228ce3235fce6feef8d82f3
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1537667
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Tested-by: Shu Zhong <shuz@nvidia.com>
2017-08-11 14:57:08 -07:00
Sunny He
96615351ad gpu: nvgpu: gv11b: Reorg mm HAL init
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
mm sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: Ic2c7d56e552645f2125d9c60a817967be1e8e765
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533355
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2017-08-11 14:16:53 -07:00
Seema Khowala
aa05648fd6 gpu: nvgpu: gv11b: set up for enabling/handling hub intr
-implement mm ops init_mm_setup_hw
 This will also call *fault*setup* that will do s/w and h/w
 set up required to get mmu fault info

-implement s/w set up for copying mmu faults
 Two shadow fault buffers are pre allocated which will be used to copy
 fault info. One for copying from fault snap registers/nonreplayable h/w
 fault buffers and one for replay h/w fault buffers

-implement s/w set up for buffering mmu faults
 Replayable/Non-replayable fault buffers are mapped in BAR2
 virtual/physical address space. These buffers are circular buffers in
 terms of address calculation. Currently there are num host channels
 buffers

-configure h/w for buffering mmu faults
 if s/w set up is successful, configure h/w registers to enable
 buffered mode of mmu faults

-if both s/w and h/w set up are successful, enable corresponding
 hub interrupts

-implement new ops, fault_info_buf_deinit
 This will be called during gk20a_mm_destroy to disable hub intr and
 de-allocate shadow fault buf that is used to copy mmu fault info during
 mmu fault handling

-implement mm ops remove_bar2_vm
 This will also unmap and free fault buffers mapped in BAR2 if fault
 buffers were allocated

JIRA GPUT19X-7
JIRA GPUT19X-12

Change-Id: I53a38eddbb0a50a1f2024600583f2aae1f1fba6d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1492682
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
GVS: Gerrit_Virtual_Submit
2017-07-08 11:35:48 -07:00
Seshendra Gadagottu
c84ddceda6 gpu: nvgpu: gv11b: sm priv reg related changes
Included all basic ops for gv11b and updated
sm related functions to include new priv register
addresses.

Bug 1735757

Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5
Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1126961
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
2016-04-16 07:48:28 -07:00