4 Commits

Author	SHA1	Message	Date
seshendra Gadagottu	65513bc33d	gpu: nvgpu: gv11b: update thermal settings ... For gv11b, update thermal settings as per hw POR: 1.Created gv11b specific HAL for init_therm_setup_hw 2.Update steps for gradual slowdown to 1x,1.5x,2x,4x,8x,16x,32x. 3.Modified gradual step duration cycles to 4. Bug 200365110 Change-Id: I93c28a3394857aacdf3d304103c9e7c25d4ad344 Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1616600 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>	2017-12-14 15:11:26 -08:00
Seema Khowala	f63f96866d	gpu: nvgpu: gv11b: init therm regs for pwr/clk ... init *eng_delay*, *eng_idle_filt*, *fecs_idle_filter* and *hubmmu_idle_filter* in therm regs. Change-Id: I4ab5374084e993cd96ef28ace87b6013b996178d Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1570556 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>	2017-10-03 13:35:48 -07:00
Sunny He	f457e808f0	gpu: nvgpu: gv11b: Reorg therm HAL initialization ... Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the therm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ic297792c4d47ffbe64cc0bd95a659a6b7f383743 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1527423 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>	2017-07-27 16:34:46 -07:00
Seshendra Gadagottu	c84ddceda6	gpu: nvgpu: gv11b: sm priv reg related changes ... Included all basic ops for gv11b and updated sm related functions to include new priv register addresses. Bug 1735757 Change-Id: Ie48651f918ee97fba00487111e4b28d6c95747f5 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/1126961 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>	2016-04-16 07:48:28 -07:00