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10 Commits

Author SHA1 Message Date
Vedashree Vidwans
c90fcbae2a gpu: nvgpu: fix MISRA Rule 2.2 no dead code 
MISRA rule 2.2 defines dead code as "operations which are executed but
removal of these operations has no effect on program behavior".
Variable initializations violate this rule if initialized value is not
used and replaced.

This patch fixes some of these reported violations.

Jira NVGPU-858

Change-Id: I694517ace8884c78c63f6346e455078d19b70b4d
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110459
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-05-02 15:56:56 -07:00
Sagar Kamble
2f3314fb9e gpu: nvgpu: address CCM deviations for pmu_cmd_post and rpc_execute 
nvgpu_pmu_cmd_post and nvgpu_pmu_rpc_execute CCM values were higher than
10. Address the same by moving cmd checks to pmu_validate_cmd and right
cleanup in nvgpu_pmu_rpc_execute.

JIRA NVGPU-3194

Change-Id: I5357a2469b256d4540881ad23f592dcee725511b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101942
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 14:17:52 -07:00
Sagar Kamble
6d1dc93117 gpu: nvgpu: address CCM deviations for pmu_cmd_payload_setup 
pmu_cmd_payload_setup CCM value was higher than 10. Prepare new
functions pmu_cmd_in_payload_setup and pmu_cmd_out_payload_setup
to seggregate the setup.

JIRA NVGPU-3194

Change-Id: I846111d0f783211f1ec934d9f39a7e5993af3a62
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101941
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 14:17:42 -07:00
Sagar Kamble
17c479ac47 gpu: nvgpu: address CCM deviations for pmu_validate_cmd 
pmu_validate_cmd CC value was higher than 10. Prepare new functions
pmu_validate_in_out_payload and pmu_validate_rpc_payload to
seggregate the validation checks.

JIRA NVGPU-3194

Change-Id: Ic1532b42c08a00d990077e71e1a13a4382be88d9
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2101940
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-26 14:17:33 -07:00
Mahantesh Kumbar
678cfdc608 gpu: nvgpu: move sys/vid alloc functions to allocator unit 
currently sys/vid surface alloc/free as part of pmu.c which
adds circular dependency between different units within PMU,
so moved to allocator unit as these functions perform memory
allocation/free from sys/vid mem.

JIRA NVGPU-1972

Change-Id: Ib7fc60ba74b56ea59f92f5d553dec7c83b0c72f2
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2094838
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-25 16:25:20 -07:00
Mahantesh Kumbar
9108ae3c62 gpu: nvgpu: create PMU FW unit 
Created PMU fw unit to hold PMU RTOS f/w specific ops, images,
flags & command arguments needed for PMU RTOS ucode support.

Moved PMU fw ops from gk20a.gpu_ops to pmu.fw.ops as these ops
are needed to support different version of PMU fw version for
different chips

JIRA NVGPU-1955

Change-Id: I51385d8c20524431f07cba3378676464663deb20
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2090769
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-24 02:34:20 -07:00
Sagar Kamble
bcbc87dc2e gpu: nvgpu: move pmu interface headers to include/nvgpu/pmu 
Interface header files for PMU features are now moved under PMU header
files directory include/nvgpu/pmu. And fix bulk of coding style issues.
Update header file names and guards.

JIRA NVGPU-1971

Change-Id: Idf53fc09d8928d1b0a1cd16eef886de010dae06b
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2093006
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-13 12:33:52 -07:00
Mahantesh Kumbar
a22a9c2bcf gpu: nvgpu: create PMU super surface unit 
Created PMU super surface unit & moved structs/functions related to
super surface under a unit, separated super surface structs into
private/public based on its usage/access, made changes to supper
surface dependent files to reflect supper surface changes
respective to unit.

JIRA NVGPU-3045

Change-Id: I6ac426052eb60f00b432d9533460aa0afd939fe3
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2088405
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-08 04:16:16 -07:00
Abdul Salam
179e3cf84a gpu: nvpgu: Fix exit path of PMU and clk_arb 
This patch fixes below two issues.
1.Currently clk arb exit is called after GPU registers are released.
  This causes crash when clk arb WQ accesses GPU HW register for status.
  The ideal way is to exit the clk_arb which removes the WQ from running
  before calling lockout register.
2.Check if dGPU is dying during processing of PMU Commands.
  This prevents race condition when PMU is waiting for response and device
  is shutdown.

Bug 200488054

Change-Id: I812b07af7db4494d5ea2ed6197742ceb23d30a4b
Signed-off-by: Abdul Salam <absalam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2081916
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-08 03:06:43 -07:00
Sagar Kamble
16fdf8351b gpu: nvgpu: move sources to pmu ipc element 
pmu command, message, queues, sequences are part of pmu's infrastructure
for IPC. Create common/pmu/ipc folder and move all these sources there.

JIRA NVGPU-1970

Change-Id: If8c80adff93a1bf9e601f1734628c5eaa09dc3ef
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2079147
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2019-04-05 05:06:38 -07:00