Commit Graph

21 Commits

Author SHA1 Message Date
Scott Long
a139172130 gpu: nvgpu: mm: fix misra 2.7 violation
Advisory Rule 2.7 states that there should be no unused
parameters in functions.

This patch removes the unused struct gk20a pointer from
the nvgpu_aperture_str() function.

Jira NVGPU-3178

Change-Id: Ied7fed13e44f1083e7477a5d6fb9facafca838de
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2174883
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-08-14 15:17:14 -07:00
Vedashree Vidwans
6baf9fce31 gpu: nvgpu: follow-up to update variable name
This patch modifies variable name to reflect correct intent.

Jira NVGPU-3858

Change-Id: I9fe208e4e5627085bb0dd0a41fb5e5266c5713b0
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2168624
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-08-09 16:26:34 -07:00
Vedashree Vidwans
8a691fcf6c gpu: nvgpu: fix CERT-C violations in mm
INT30-C requires that unsigned integer operations do not wrap.
INT31-C requires checking that data isn't misinterpreted after casting.
INT32-C requires that signed operations do not overflow.

Jira NVGPU-3882

Change-Id: I6b4c1769ec85919f8ec2aa183cba3b7c0ffa1e97
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2166124
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-08-05 00:45:53 -07:00
Scott Long
c6b6c9b3e2 gpu: nvgpu: mm: remove misra rule 8.11 violations
Eliminate Advisory Rule 8.11 violations in gmmu_gk20a.h by
removing extern declarations of gk20a_mm_levels_64k[] and
gk20a_mm_levels_128k[].

Advisory Rule 8.11 states when an array with external linkage
is declared, its size should be explicitly specified.

Jira NVGPU-3178

Change-Id: I452a571e0561edbd9f8cd856775563587c201d40
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2162273
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-07-30 09:56:36 -07:00
Vedashree Vidwans
afae2efc23 gpu: nvgpu: fix MISRA errors in nvgpu.hal.mm
Rule 8.6 requires each identifier with external linkage to have exactly
one external definitions.
Rule 10.x necessitates operands to have essential type; left and right
operands should be of same width and type.
Rule 14.3 doesn't allow controlling expressions to be invariant;
ensuring that all conditions are possible.

Jira NVGPU-3858

Change-Id: I043a3836c4a2cb9c5a52d3053516c517389f55a2
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2162295
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-07-29 12:45:40 -07:00
Vedashree Vidwans
9a0e041602 gpu: nvgpu: fix MISRA errors in hal.mm.gmmu_fusa
Fix MISRA errors in hal/mm/gmmu/gmmu_gp10b_fusa.c

Rule 10.6 forbids assignment of u32 expression to u64 target.
This patch fixes this rule by casting the expression to u64.

Rule 20.6 doesn't allow use of preprocessor directives within a macro.
To resolve this patch moves the preprocessor directive before the macro
function call.

Jira NVGPU-3806

Change-Id: Ib7ddf746c801be62d3dd90a6ab7e27c690a60dc6
Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2152065
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-07-12 15:56:08 -07:00
Philip Elcan
1eafda5a62 gpu: nvgpu: mm: fix CERT-C bugs in gmmu HAL
Fix CERT-C INT-30 and INT-31 violations in nvgpu.hal.mm.gmmu by using
safe ops.

JIRA NVGPU-3637

Change-Id: I45d8cbe5afb05ca6406cb6eb056c3d0929eff21d
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2146986
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-07-03 21:45:36 -07:00
Nicolas Benech
9a4ad88f21 gpu: nvgpu: hal: split MM-related HALs based on FUSA
This patch moves MM HALs that are guaranteed to be functionaly safe
into _fusa.c files. HALs that are not part of FUSA are not compiled
anymore when the safety profile is enabled.

Given a HAL source file:
- it may contain only FUSA code, in that case the source file is
  simply renamed with the _fusa postfix.
- it may contain only non-FUSA code, in that case the file is left
  as-is
- it may contain a mix, in that case the original file will now only
  contain non-FUSA code, and all FUSA code will be moved into a new
  source file with the _fusa postfix.

JIRA NVGPU-3690

Change-Id: I44c604aef2d72252abb7da1c0ef1210d71a0efa7
Signed-off-by: Nicolas Benech <nbenech@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2140895
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-27 01:36:07 -07:00
Sagar Kamble
556ddaf9a3 gpu: nvgpu: add support for removing comptags and cbc from safety build
Safety build does not support compression. This patch adds support to
compile out compression related changes - comptags, cbc.

JIRA NVGPU-3532

Change-Id: I20e4ca7df46ceec175b903a6a62dff141140e787
Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125473
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-06-13 10:55:27 -07:00
Philip Elcan
66c79f3bb3 gpu: nvgpu: mm: use u64 for get_mmu_levels()
Change the big_page_size parameter for the HAL API get_mmu_levels from
u32 to u64. This eliminates a CERT-C INT31 violation in page_table.c for
casting without checking the value.

JIRA NVGPU-3515

Change-Id: If001407666acd21733017f420e615ae6bd6d929c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2125026
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-29 12:59:40 -07:00
Thomas Fleury
99bdda5846 gpu: nvgpu: fix MISRA 21.2 violations in nvgpu.hal.mm.gmmu
Renamed the following functions to fix MISRA 21.2 violations:
- __update_pte -> update_pte
- __update_pte_sparse -> update_pte_sparse

Jira NVGPU-3284

Change-Id: Ic2281254f362ca261ab66562a4160acd3bf7ebc2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119617
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-16 10:58:11 -07:00
Thomas Fleury
56718737d9 gpu: nvgpu: fix MISRA 15.7 violations in nvgpu.hal.mm.gmmu
Refactored if / else statements in nvgpu.hal.mm.gmmu
to avoid "else if" with no terminating "else" statement.

Jira NVGPU-3284

Change-Id: Id0a5901f6e74ab1b6539f8b907a4e8fdf3c1396c
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119616
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-16 10:58:01 -07:00
Thomas Fleury
8a9d329468 gpu: nvgpu: fix MISRA 10.3 violations in nvgpu.hal.mm.gmmu
Fixed MISRA 10.3 violations by using explicit casts, and
changing essential types.

Jira NVGPU-3284

Change-Id: If16c09a5100a9437e3e22bc53a81d3d1687d5cb1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119615
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-16 10:57:52 -07:00
Alex Waterman
c053bc0226 gpu: nvgpu: Move gv11b MMU fault handling to HAL
Move the gv11b MMU fault handling code into a new mm.mmu_fault HAL.
Also move the existing gmmu_mmu_fault HAL code into this HAL as they
are basically the same logical entity.

JIRA NVGPU-2042
JIRA NVGPU-1313

Change-Id: I41d3e180c762f191d4de3237e9052bdc456f9e4c
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109693
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-03 16:26:07 -07:00
Seema Khowala
170d7464d6 gpu: nvgpu: move fifo_gk20a.[ch] to hal/fifo
Move fifo_gk20a struct to fifo.h
Move fifo_gk20a.[ch] to hal/fifo

Add missing includes for fifo subunits.

JIRA NVGPU-2012

Change-Id: I8bf5402bd5a9f8ff9f6a818cee553b57e117f3bc
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109012
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-02 23:40:42 -07:00
Seema Khowala
39070c653f gpu: nvgpu: move FIFO_INVAL_* out of fifo_gk20a.h
Move and rename
FIFO_INVAL_ENGINE_ID -> NVGPU_INVALID_ENG_ID
FIFO_INVAL_TSG_ID -> NVGPU_INVALID_TSG_ID
FIFO_INVAL_RUNLIST_ID -> NVGPU_INVALID_RUNLIST_ID
FIFO_INVAL_SYNCPT_ID -> NVGPU_INVALID_SYNCPT_ID
FIFO_INVAL_CHANNEL_ID -> NVGPU_INVALID_CHANNEL_ID

JIRA NVGPU-2012

Change-Id: Ic4cc16ece64d85e22f16e4d28dcfd0c187bb65f3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109011
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-02 23:40:26 -07:00
Alex Waterman
6c2c4181ae gpu: nvgpu: Create hal.mm.mm for misc MM HALs
There are many miscellaneous HALs for various MM related functionality.
This patch aims to migrate all the remaining MM code from the <chip>/
mm_<chip>.[ch] files in HAL files under hal/.

Much of this is fairly straightforward copy/paste and updates to the
HAL init files.

The exception to that is the move of the left over gv11b MMU fault
handling code in mm_gv11b.c. Having both a hal/mm/mm/mm_gv11b.c and
a gv11b/mm_gv11b.c file causes tmake to choke so the gv11b/mm_gv11b.c
file was moved to gv11b/mmu_fault_gv11b.c. This will be cleaned up in
a subsequent patch.

JIRA NVGPU-2042

Change-Id: I12896de865d890a61afbcb71159cff486119ffb8
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109050
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-05-01 15:06:57 -07:00
Seema Khowala
1a85ecf1ed gpu: nvgpu: add include/nvgpu/mmu_fault.h
Move mmu_fault_info struct from mm.h to mmu_fault.h

Rename and move below hash defines to mmu_fault.h
NVGPU_MM_MMU_FAULT_TYPE_OTHER_AND_NONREPLAY -> NVGPU_MMU_FAULT_NONREPLAY_INDX
NVGPU_MM_MMU_FAULT_TYPE_REPLAY -> NVGPU_MMU_FAULT_REPLAY_INDX
FAULT_TYPE_NUM -> NVGPU_MMU_FAULT_TYPE_NUM
NVGPU_FB_MMU_FAULT_NONREPLAY_REG_INDEX -> NVGPU_MMU_FAULT_NONREPLAY_REG_INDX
NVGPU_FB_MMU_FAULT_REPLAY_REG_INDEX -> NVGPU_MMU_FAULT_REPLAY_REG_INDX
NVGPU_FB_MMU_FAULT_BUF_DISABLED -> NVGPU_MMU_FAULT_BUF_DISABLED
NVGPU_FB_MMU_FAULT_BUF_ENABLED -> NVGPU_MMU_FAULT_BUF_ENABLED

JIRA NVGPU-1313

Change-Id: I3d4d56f881a5c3856c005db6dc7d850be4bc041d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107772
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-30 12:45:33 -07:00
Seema Khowala
906fd57c18 gpu: nvgpu: add fb/gmmu mmu_fault_gv11b.[ch]
Move mmu fault related functions from fb_gv11b.c
to hal/fb/fb_mmu_fault_gv11b.c and hal/mm/gmmu/gmmu_mmu_fault_gv11b.c

Rename
mmfault to mmufault
fb_gv11b_write_mmu_fault_buffer_lo_hi -> gv11b_fb_write_mmu_fault_buffer_lo_hi
fb_gv11b_read_mmu_fault_buffer_get -> gv11b_fb_read_mmu_fault_buffer_get
fb_gv11b_read_mmu_fault_buffer_put -> gv11b_fb_read_mmu_fault_buffer_put
fb_gv11b_read_mmu_fault_buffer_size -> gv11b_fb_read_mmu_fault_buffer_size
fb_gv11b_write_mmu_fault_buffer_size -> gv11b_fb_write_mmu_fault_buffer_size
fb_gv11b_read_mmu_fault_addr_lo_hi -> gv11b_fb_read_mmu_fault_addr_lo_hi
fb_gv11b_read_mmu_fault_inst_lo_hi -> gv11b_fb_read_mmu_fault_inst_lo_hi
fb_gv11b_read_mmu_fault_info -> gv11b_fb_read_mmu_fault_info
fb_gv11b_read_mmu_fault_status -> gv11b_fb_read_mmu_fault_status
fb_gv11b_write_mmu_fault_status -> gv11b_fb_write_mmu_fault_status
gv11b_fb_parse_mmfault -> gv11b_fb_parse_mmu_fault_info
gv11b_fb_print_fault_info -> gv11b_fb_mmu_fault_info_dump

Rename and move to gmmu
gv11b_fb_parse_mmu_fault_info -> gv11b_gmmu_parse_mmu_fault_info
gv11b_fb_handle_mmu_nonreplay_replay_fault -> gv11b_gmmu_handle_mmu_nonreplay_replay_fault
gv11b_fb_handle_mmu_fault_common -> gv11b_gmmu_handle_mmu_fault_common
gv11b_fb_handle_other_fault_notify -> gv11b_gmmu_handle_other_fault_notify

JIRA NVGPU-1313

Change-Id: Ia69a0b6b50347d11764e3ff34a5ea67ea8d64915
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2107771
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-30 12:45:19 -07:00
Alex Waterman
00d7b53b73 gpu: nvgpu: Move remaining GMMU HAL code to hal/mm/gmmu/
Move the remaining GMMU HAL related code from the gm20b/, gp10b/,
and gv11b/ directories to new gmmu hal source files.

Also update all makefiles and HAL init code to refelct the new
location of the headers and source code.

JIRA NVGPU-2042

Change-Id: Ic9b85cc547bd0f994ad11042fc4093c517327399
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2103672
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-26 09:36:26 -07:00
Alex Waterman
efbe371fd5 gpu: nvgpu: Create hal/mm/gmmu and move gk20a GMMU code
Make a hal/mm/gmmu sub-unit for the GMMU HAL code. Also move the
gk20a specific HAL code there. gp10b will happen in the next patch.

This change also updates all the GMMU related HAL usage, of which
there is quite a bit. Generally the only change is a .gmmu needs to
be inserted into the HAL path. Each HAL init was also updated.

JIRA NVGPU-2042

Change-Id: I6c46bdfddb8e021f56103d9457fb3e2a226f8947
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2099693
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
2019-04-23 12:45:54 -07:00