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gpu: nvgpu: fix MISRA 21.2 violations in nvgpu.hal.mm.gmmu

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Renamed the following functions to fix MISRA 21.2 violations:
- __update_pte -> update_pte
- __update_pte_sparse -> update_pte_sparse

Jira NVGPU-3284

Change-Id: Ic2281254f362ca261ab66562a4160acd3bf7ebc2
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2119617
GVS: Gerrit_Virtual_Submit
Reviewed-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-by: Vinod Gopalakrishnakurup <vinodg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Thomas Fleury
2019-05-15 09:48:13 -07:00
committed by mobile promotions
parent 56718737d9
commit 99bdda5846
1 changed files with 4 additions and 4 deletions
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8
drivers/gpu/nvgpu/hal/mm/gmmu/gmmu_gk20a.c
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@@ -100,13 +100,13 @@ static void update_gmmu_pde_locked(struct vm_gk20a *vm,
nvgpu_pd_write(g, &vm->pdb, (size_t)pd_offset + (size_t)1, pde_v[1]);
}
static void __update_pte_sparse(u32 *pte_w)
static void update_pte_sparse(u32 *pte_w)
{
pte_w[0] = gmmu_pte_valid_false_f();
pte_w[1] |= gmmu_pte_vol_true_f();
}
static void __update_pte(struct vm_gk20a *vm,
static void update_pte(struct vm_gk20a *vm,
u32 *pte_w,
u64 phys_addr,
struct nvgpu_gmmu_attrs *attrs)
@@ -189,10 +189,10 @@ static void update_gmmu_pte_locked(struct vm_gk20a *vm,
}
if (phys_addr != 0ULL) {
__update_pte(vm, pte_w, phys_addr, attrs);
update_pte(vm, pte_w, phys_addr, attrs);
} else {
if (attrs->sparse) {
__update_pte_sparse(pte_w);
update_pte_sparse(pte_w);
}
}